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ARD2
1.00 for Rev B. Hardware
Airbag Reference Demonstrator using MPC5604P
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ARD2
1.00 for Rev B. Hardware
Airbag Reference Demonstrator using MPC5604P
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00001 /***************************************************************** 00002 * PROJECT : MPC560xB, MPC560xP & MPC560xS 00003 * SPC560xB, SPC560xP & SPC560xS 00004 * FILE : jdp.h 00005 * 00006 * DESCRIPTION : This is the header file describing the register 00007 * set for the named projects. 00008 * 00009 * COPYRIGHT :(c) 2008, Freescale & STMicroelectronics 00010 * 00011 * VERSION : 01.04 00012 * DATE : 05.11.2008 00013 * MODIFIED : 18.03.2009 00014 * AUTHOR : b04629 00015 * HISTORY : Modified to support ADC on Pictus cut 2 - do not distribute! (ttz778) 00016 * HISTORY : Modified to support CRC on Pictus cut 2 - do not distribute! (r60321) 00017 * HISTORY : Modified to support DSPI0 CS7&8 and new FlexPWM naming on Pictus cut 2 (r60321) 00018 * HISTORY : Modified to update MIDR1&2 registers and LINCR1-SFTM and LINESR-BDEF bit on Pictus (r60321) 00019 * HISTORY : Modified to update RGM, CFLASH & DFLASH registers and FlexCAN & CTU Registers on Pictus (r60321) 00020 */ 00021 /* **********************************************************************************/ 00022 /* * THIS HEADER FILE IS ONLY INTENDED AS AN EXAMPLE CODE FOR THE */ 00023 /* * JDP DEVICES AND HAS ONLY BEEN GIVEN A MIMIMUM LEVEL OF TEST. */ 00024 /* * IT IS PROVIDED 'AS SEEN' WITH NO GUARANTEES AND NO PROMISE */ 00025 /* * OF SUPPORT. USE AT YOUR OWN RISK !! */ 00026 /* **********************************************************************************/ 00027 /***************************************************************** 00028 * Example instantiation and use: 00029 * 00030 * <MODULE>.<REGISTER>.B.<BIT> = 1; 00031 * <MODULE>.<REGISTER>.R = 0x10000000; 00032 * 00033 ******************************************************************/ 00034 00035 #ifndef _JDP_H_ 00036 #define _JDP_H_ 00037 00038 #include "typedefs.h" 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 #ifdef __MWERKS__ 00045 #pragma push 00046 #pragma ANSI_strict off 00047 #endif 00048 /****************************************************************************/ 00049 /* MODULE : ADC */ 00050 /****************************************************************************/ 00051 struct ADC_tag { 00052 00053 union { 00054 vuint32_t R; 00055 struct { 00056 vuint32_t OWREN:1; 00057 vuint32_t WLSIDE:1; 00058 vuint32_t MODE:1; 00059 vuint32_t EDGLEV:1; 00060 vuint32_t TRGEN:1; 00061 vuint32_t EDGE:1; 00062 vuint32_t XSTRTEN:1; 00063 vuint32_t NSTART:1; 00064 vuint32_t:1; 00065 vuint32_t JTRGEN:1; 00066 vuint32_t JEDGE:1; 00067 vuint32_t JSTART:1; 00068 vuint32_t:2; 00069 vuint32_t CTUEN:1; 00070 vuint32_t:8; 00071 vuint32_t ADCLKSEL:1; 00072 vuint32_t ABORTCHAIN:1; 00073 vuint32_t ABORT:1; 00074 vuint32_t ACK0:1; 00075 vuint32_t OFFREFRESH:1; 00076 vuint32_t OFFCANC:1; 00077 vuint32_t:2; 00078 vuint32_t PWDN:1; 00079 } B; 00080 } MCR; /* MAIN CONFIGURATION REGISTER */ 00081 00082 union { 00083 vuint32_t R; 00084 struct { 00085 vuint32_t:7; 00086 vuint32_t NSTART:1; 00087 vuint32_t JABORT:1; 00088 vuint32_t:2; 00089 vuint32_t JSTART:1; 00090 vuint32_t:3; 00091 vuint32_t CTUSTART:1; 00092 vuint32_t CHADDR:7; 00093 vuint32_t:3; 00094 vuint32_t ACK0:1; 00095 vuint32_t OFFREFRESH:1; 00096 vuint32_t OFFCANC:1; 00097 vuint32_t ADCSTATUS:3; 00098 } B; 00099 } MSR; /* MAIN STATUS REGISTER */ 00100 00101 int32_t ADC_reserved1[2]; /* (0x008 - 0x00F)/4 = 0x02 */ 00102 00103 union { 00104 vuint32_t R; 00105 struct { 00106 vuint32_t:25; 00107 vuint32_t OFFCANCOVR:1; 00108 vuint32_t EOFFSET:1; 00109 vuint32_t EOCTU:1; 00110 vuint32_t JEOC:1; 00111 vuint32_t JECH:1; 00112 vuint32_t EOC:1; 00113 vuint32_t ECH:1; 00114 } B; 00115 } ISR; /* INTERRUPT STATUS REGISTER */ 00116 00117 union { 00118 vuint32_t R; 00119 struct { 00120 vuint32_t EOC31:1; 00121 vuint32_t EOC30:1; 00122 vuint32_t EOC29:1; 00123 vuint32_t EOC28:1; 00124 vuint32_t EOC27:1; 00125 vuint32_t EOC26:1; 00126 vuint32_t EOC25:1; 00127 vuint32_t EOC24:1; 00128 vuint32_t EOC23:1; 00129 vuint32_t EOC22:1; 00130 vuint32_t EOC21:1; 00131 vuint32_t EOC20:1; 00132 vuint32_t EOC19:1; 00133 vuint32_t EOC18:1; 00134 vuint32_t EOC17:1; 00135 vuint32_t EOC16:1; 00136 vuint32_t EOC15:1; 00137 vuint32_t EOC14:1; 00138 vuint32_t EOC13:1; 00139 vuint32_t EOC12:1; 00140 vuint32_t EOC11:1; 00141 vuint32_t EOC10:1; 00142 vuint32_t EOC9:1; 00143 vuint32_t EOC8:1; 00144 vuint32_t EOC7:1; 00145 vuint32_t EOC6:1; 00146 vuint32_t EOC5:1; 00147 vuint32_t EOC4:1; 00148 vuint32_t EOC3:1; 00149 vuint32_t EOC2:1; 00150 vuint32_t EOC1:1; 00151 vuint32_t EOC0:1; 00152 } B; 00153 } CEOCFR[3]; /* Channel Pending Register 0 */ 00154 00155 union { 00156 vuint32_t R; 00157 struct { 00158 vuint32_t:25; //One bit added 00159 vuint32_t MSKOFFCANCOVR:1; //Moved up 00160 vuint32_t MSKEOFFSET:1; //Moved up 00161 vuint32_t MSKEOCTU:1; //New for cut 2 00162 vuint32_t MSKJEOC:1; 00163 vuint32_t MSKJECH:1; 00164 vuint32_t MSKEOC:1; 00165 vuint32_t MSKECH:1; 00166 } B; 00167 } IMR; /* INTERRUPT MASK REGISTER */ 00168 00169 union { 00170 vuint32_t R; 00171 struct { 00172 vuint32_t CIM31:1; 00173 vuint32_t CIM30:1; 00174 vuint32_t CIM29:1; 00175 vuint32_t CIM28:1; 00176 vuint32_t CIM27:1; 00177 vuint32_t CIM26:1; 00178 vuint32_t CIM25:1; 00179 vuint32_t CIM24:1; 00180 vuint32_t CIM23:1; 00181 vuint32_t CIM22:1; 00182 vuint32_t CIM21:1; 00183 vuint32_t CIM20:1; 00184 vuint32_t CIM19:1; 00185 vuint32_t CIM18:1; 00186 vuint32_t CIM17:1; 00187 vuint32_t CIM16:1; 00188 vuint32_t CIM15:1; 00189 vuint32_t CIM14:1; 00190 vuint32_t CIM13:1; 00191 vuint32_t CIM12:1; 00192 vuint32_t CIM11:1; 00193 vuint32_t CIM10:1; 00194 vuint32_t CIM9:1; 00195 vuint32_t CIM8:1; 00196 vuint32_t CIM7:1; 00197 vuint32_t CIM6:1; 00198 vuint32_t CIM5:1; 00199 vuint32_t CIM4:1; 00200 vuint32_t CIM3:1; 00201 vuint32_t CIM2:1; 00202 vuint32_t CIM1:1; 00203 vuint32_t CIM0:1; 00204 } B; 00205 } CIMR[3]; /* Channel Interrupt Mask Register 0 */ 00206 00207 union { 00208 vuint32_t R; 00209 struct { 00210 vuint32_t:24; 00211 vuint32_t WDG3H:1; 00212 vuint32_t WDG2H:1; 00213 vuint32_t WDG1H:1; 00214 vuint32_t WDG0H:1; 00215 vuint32_t WDG3L:1; 00216 vuint32_t WDG2L:1; 00217 vuint32_t WDG1L:1; 00218 vuint32_t WDG0L:1; 00219 } B; 00220 } WTISR; /* WATCHDOG INTERRUPT THRESHOLD REGISTER was WDGTHR */ 00221 00222 union { 00223 vuint32_t R; 00224 struct { 00225 vuint32_t:24; 00226 vuint32_t MSKWDG3H:1; 00227 vuint32_t MSKWDG2H:1; 00228 vuint32_t MSKWDG1H:1; 00229 vuint32_t MSKWDG0H:1; 00230 vuint32_t MSKWDG3L:1; 00231 vuint32_t MSKWDG2L:1; 00232 vuint32_t MSKWDG1L:1; 00233 vuint32_t MSKWDG0L:1; 00234 } B; 00235 } WTIMR; /* WATCHDOG INTERRUPT MASK REGISTER was IMWDGTHR */ 00236 00237 int32_t ADC_reserved2[2]; /* (0x038 - 0x03F)/4 = 0x02 */ 00238 00239 union { 00240 vuint32_t R; 00241 struct { 00242 vuint32_t:30; //was 16 00243 vuint32_t DCLR:1; //moved 00244 vuint32_t DMAEN:1; //moved 00245 } B; 00246 } DMAE; /* DMAE REGISTER */ 00247 00248 union { 00249 vuint32_t R; 00250 struct { 00251 vuint32_t DMA31:1; //was unused [16] 00252 vuint32_t DMA30:1; 00253 vuint32_t DMA29:1; 00254 vuint32_t DMA28:1; 00255 vuint32_t DMA27:1; 00256 vuint32_t DMA26:1; 00257 vuint32_t DMA25:1; 00258 vuint32_t DMA24:1; 00259 vuint32_t DMA23:1; 00260 vuint32_t DMA22:1; 00261 vuint32_t DMA21:1; 00262 vuint32_t DMA20:1; 00263 vuint32_t DMA19:1; 00264 vuint32_t DMA18:1; 00265 vuint32_t DMA17:1; 00266 vuint32_t DMA16:1; 00267 vuint32_t DMA15:1; 00268 vuint32_t DMA14:1; 00269 vuint32_t DMA13:1; 00270 vuint32_t DMA12:1; 00271 vuint32_t DMA11:1; 00272 vuint32_t DMA10:1; 00273 vuint32_t DMA9:1; 00274 vuint32_t DMA8:1; 00275 vuint32_t DMA7:1; 00276 vuint32_t DMA6:1; 00277 vuint32_t DMA5:1; 00278 vuint32_t DMA4:1; 00279 vuint32_t DMA3:1; 00280 vuint32_t DMA2:1; 00281 vuint32_t DMA1:1; 00282 vuint32_t DMA0:1; 00283 } B; 00284 } DMAR[3]; /* DMA REGISTER was [6] */ 00285 00286 union { 00287 vuint32_t R; 00288 struct { 00289 vuint32_t:16; 00290 vuint32_t THREN:1; 00291 vuint32_t THRINV:1; 00292 vuint32_t THROP:1; 00293 vuint32_t:6; 00294 vuint32_t THRCH:7; 00295 } B; 00296 } TRC[4]; /* ADC THRESHOLD REGISTER REGISTER */ 00297 00298 union { 00299 vuint32_t R; 00300 struct { //were in TRA & TRB 00301 vuint32_t:4; 00302 vuint32_t THRH:12; 00303 vuint32_t:4; 00304 vuint32_t THRL:12; 00305 } B; 00306 } THRHLR[4]; /* THRESHOLD REGISTER */ 00307 00308 union { 00309 vuint32_t R; 00310 struct { //were in TRAALT & TRBALT 00311 vuint32_t:4; 00312 vuint32_t THRH:12; 00313 vuint32_t:4; 00314 vuint32_t THRL:12; 00315 } B; 00316 } THRALT[4]; /* ADC THRESHOLD REGISTER REGISTER */ 00317 00318 union { 00319 vuint32_t R; 00320 struct { 00321 vuint32_t:25; //was 26 00322 vuint32_t PREVAL2:2; 00323 vuint32_t PREVAL1:2; 00324 vuint32_t PREVAL0:2; 00325 vuint32_t PREONCE:1; 00326 } B; 00327 } PSCR; /* PRESAMPLING CONTROL REGISTER was PREREG */ 00328 00329 union { 00330 vuint32_t R; 00331 struct { 00332 vuint32_t PRES31:1; //was reserved 16 00333 vuint32_t PRES30:1; 00334 vuint32_t PRES29:1; 00335 vuint32_t PRES28:1; 00336 vuint32_t PRES27:1; 00337 vuint32_t PRES26:1; 00338 vuint32_t PRES25:1; 00339 vuint32_t PRES24:1; 00340 vuint32_t PRES23:1; 00341 vuint32_t PRES22:1; 00342 vuint32_t PRES21:1; 00343 vuint32_t PRES20:1; 00344 vuint32_t PRES19:1; 00345 vuint32_t PRES18:1; 00346 vuint32_t PRES17:1; 00347 vuint32_t PRES16:1; 00348 vuint32_t PRES15:1; 00349 vuint32_t PRES14:1; 00350 vuint32_t PRES13:1; 00351 vuint32_t PRES12:1; 00352 vuint32_t PRES11:1; 00353 vuint32_t PRES10:1; 00354 vuint32_t PRES9:1; 00355 vuint32_t PRES8:1; 00356 vuint32_t PRES7:1; 00357 vuint32_t PRES6:1; 00358 vuint32_t PRES5:1; 00359 vuint32_t PRES4:1; 00360 vuint32_t PRES3:1; 00361 vuint32_t PRES2:1; 00362 vuint32_t PRES1:1; 00363 vuint32_t PRES0:1; 00364 } B; 00365 } PSR[3]; /* PRESAMPLING REGISTER was PRER[6]*/ 00366 00367 int32_t ADC_reserved3[1]; /* (0x090 - 0x093)/4 = 0x01 */ 00368 00369 union { 00370 vuint32_t R; 00371 struct { 00372 vuint32_t:16; 00373 vuint32_t INPLATCH:1; 00374 vuint32_t:1; 00375 vuint32_t OFFSHIFT:2; 00376 vuint32_t:1; 00377 vuint32_t INPCMP:2; 00378 vuint32_t:1; 00379 vuint32_t INPSAMP:8; 00380 } B; 00381 } CTR[3]; /* CONVERSION TIMING REGISTER was CT[3] */ 00382 00383 int32_t ADC_reserved4[1]; /* (0x0A0 - 0x0A3)/4 = 0x01 */ 00384 00385 union { 00386 vuint32_t R; 00387 struct { 00388 vuint32_t CH31:1; //was reserved 16 00389 vuint32_t CH30:1; 00390 vuint32_t CH29:1; 00391 vuint32_t CH28:1; 00392 vuint32_t CH27:1; 00393 vuint32_t CH26:1; 00394 vuint32_t CH25:1; 00395 vuint32_t CH24:1; 00396 vuint32_t CH23:1; 00397 vuint32_t CH22:1; 00398 vuint32_t CH21:1; 00399 vuint32_t CH20:1; 00400 vuint32_t CH19:1; 00401 vuint32_t CH18:1; 00402 vuint32_t CH17:1; 00403 vuint32_t CH16:1; 00404 vuint32_t CH15:1; 00405 vuint32_t CH14:1; 00406 vuint32_t CH13:1; 00407 vuint32_t CH12:1; 00408 vuint32_t CH11:1; 00409 vuint32_t CH10:1; 00410 vuint32_t CH9:1; 00411 vuint32_t CH8:1; 00412 vuint32_t CH7:1; 00413 vuint32_t CH6:1; 00414 vuint32_t CH5:1; 00415 vuint32_t CH4:1; 00416 vuint32_t CH3:1; 00417 vuint32_t CH2:1; 00418 vuint32_t CH1:1; 00419 vuint32_t CH0:1; 00420 } B; 00421 } NCMR[3]; /* NORMAL CONVERSION MASK REGISTER was [6] */ 00422 00423 int32_t ADC_reserved5[1]; /* (0x0B0 - 0x0B3)/4 = 0x01 */ 00424 00425 union { 00426 vuint32_t R; 00427 struct { 00428 vuint32_t CH31:1; //was reserved 16 00429 vuint32_t CH30:1; 00430 vuint32_t CH29:1; 00431 vuint32_t CH28:1; 00432 vuint32_t CH27:1; 00433 vuint32_t CH26:1; 00434 vuint32_t CH25:1; 00435 vuint32_t CH24:1; 00436 vuint32_t CH23:1; 00437 vuint32_t CH22:1; 00438 vuint32_t CH21:1; 00439 vuint32_t CH20:1; 00440 vuint32_t CH19:1; 00441 vuint32_t CH18:1; 00442 vuint32_t CH17:1; 00443 vuint32_t CH16:1; 00444 vuint32_t CH15:1; 00445 vuint32_t CH14:1; 00446 vuint32_t CH13:1; 00447 vuint32_t CH12:1; 00448 vuint32_t CH11:1; 00449 vuint32_t CH10:1; 00450 vuint32_t CH9:1; 00451 vuint32_t CH8:1; 00452 vuint32_t CH7:1; 00453 vuint32_t CH6:1; 00454 vuint32_t CH5:1; 00455 vuint32_t CH4:1; 00456 vuint32_t CH3:1; 00457 vuint32_t CH2:1; 00458 vuint32_t CH1:1; 00459 vuint32_t CH0:1; 00460 } B; 00461 } JCMR[3]; /* Injected CONVERSION MASK REGISTER was ICMR[6] */ 00462 00463 union { 00464 vuint32_t R; 00465 struct { 00466 vuint32_t:15; 00467 vuint32_t OFFSETLOAD:1; //new 00468 vuint32_t:8; 00469 vuint32_t OFFSETWORD:8; 00470 } B; 00471 } OFFWR; /* OFFSET WORD REGISTER was OFFREG*/ 00472 00473 union { 00474 vuint32_t R; 00475 struct { 00476 vuint32_t:24; 00477 vuint32_t DSD:8; 00478 } B; 00479 } DSDR; /* DECODE SIGNALS DELAY REGISTER was DSD */ 00480 00481 union { 00482 vuint32_t R; 00483 struct { 00484 vuint32_t:24; 00485 vuint32_t PDED:8; //was PDD 00486 } B; 00487 } PDEDR; /* POWER DOWN DELAY REGISTER was PDD */ 00488 00489 int32_t ADC_reserved6[9]; /* (0x0CC - 0x0EF)/4 = 0x09 */ 00490 00491 union { 00492 vuint32_t R; 00493 struct { 00494 vuint32_t TEST_CTL:32; 00495 } B; 00496 } TCTLR; /* Test control REGISTER */ 00497 00498 int32_t ADC_reserved7[3]; /* (0x0F4 - 0x0FF)/4 = 0x03 */ 00499 00500 union { 00501 vuint32_t R; 00502 struct { 00503 vuint32_t:12; 00504 vuint32_t VALID:1; 00505 vuint32_t OVERW:1; 00506 vuint32_t RESULT:2; 00507 vuint32_t:4; 00508 vuint32_t CDATA:12; 00509 } B; 00510 } CDR[96]; /* Channel 0-95 Data REGISTER */ 00511 00512 }; /* end of ADC_tag */ 00513 /****************************************************************************/ 00514 /* MODULE : CANSP */ 00515 /****************************************************************************/ 00516 struct CANSP_tag { 00517 union { 00518 vuint16_t R; 00519 struct { 00520 vuint16_t RX_COMPLETE:1; 00521 vuint16_t BUSY:1; 00522 vuint16_t ACTIVE_CK:1; 00523 vuint16_t:3; 00524 vuint16_t MODE:1; 00525 vuint16_t CAN_RX_SEL:3; 00526 vuint16_t BRP:5; 00527 vuint16_t CAN_SMPLR_EN:1; 00528 } B; 00529 } CR; /* CANSP Control Register */ 00530 00531 int16_t CANSP_reserved; 00532 00533 union { 00534 vuint32_t R; 00535 } SR[12]; /* CANSP Sample Register 0 to 11 */ 00536 00537 }; /* end of CANSP_tag */ 00538 /****************************************************************************/ 00539 /* MODULE : MCM */ 00540 /****************************************************************************/ 00541 struct MCM_tag { 00542 00543 union { 00544 vuint16_t R; 00545 } PCT; /* MCM Processor Core Type Register */ 00546 00547 union { 00548 vuint16_t R; 00549 } REV; /* MCM Revision Register */ 00550 00551 int32_t MCM_reserved; 00552 00553 union { 00554 vuint32_t R; 00555 } MC; /* MCM Configuration Register */ 00556 00557 int8_t MCM_reserved1[3]; 00558 00559 union { 00560 vuint8_t R; 00561 struct { 00562 vuint8_t POR:1; 00563 vuint8_t DIR:1; 00564 vuint8_t:6; 00565 } B; 00566 } MRSR; /* MCM Miscellaneous Reset Status Register */ 00567 00568 int8_t MCM_reserved2[3]; 00569 00570 union { 00571 vuint8_t R; 00572 struct { 00573 vuint8_t ENBWCR:1; 00574 vuint8_t:3; 00575 vuint8_t PRILVL:4; 00576 } B; 00577 } MWCR; /* MCM Miscellaneous Wakeup Control Register */ 00578 00579 int32_t MCM_reserved3[2]; 00580 int8_t MCM_reserved4[3]; 00581 00582 union { 00583 vuint8_t R; 00584 struct { 00585 vuint8_t FB0AI:1; 00586 vuint8_t FB0SI:1; 00587 vuint8_t FB1AI:1; 00588 vuint8_t FB1SI:1; 00589 vuint8_t:4; 00590 } B; 00591 } MIR; /* MCM Miscellaneous Interrupt Register */ 00592 00593 int32_t MCM_reserved5; 00594 00595 union { 00596 vuint32_t R; 00597 } MUDCR; /* MCM Miscellaneous User-Defined Control Register */ 00598 00599 int32_t MCM_reserved6[6]; /* (0x040- 0x028)/4 = 0x06 */ 00600 int8_t MCM_reserved7[3]; 00601 00602 union { 00603 vuint8_t R; 00604 struct { 00605 vuint8_t:2; 00606 vuint8_t ER1BR:1; 00607 vuint8_t EF1BR:1; 00608 vuint8_t:2; 00609 vuint8_t ERNCR:1; 00610 vuint8_t EFNCR:1; 00611 } B; 00612 } ECR; /* MCM ECC Configuration Register */ 00613 00614 int8_t MCM_reserved8[3]; 00615 00616 union { 00617 vuint8_t R; 00618 struct { 00619 vuint8_t:2; 00620 vuint8_t R1BC:1; 00621 vuint8_t F1BC:1; 00622 vuint8_t:2; 00623 vuint8_t RNCE:1; 00624 vuint8_t FNCE:1; 00625 } B; 00626 } ESR; /* MCM ECC Status Register */ 00627 00628 int16_t MCM_reserved9; 00629 00630 union { 00631 vuint16_t R; 00632 struct { 00633 vuint16_t:2; 00634 vuint16_t FRC1BI:1; 00635 vuint16_t FR11BI:1; 00636 vuint16_t:2; 00637 vuint16_t FRCNCI:1; 00638 vuint16_t FR1NCI:1; 00639 vuint16_t:1; 00640 vuint16_t ERRBIT:7; 00641 } B; 00642 } EEGR; /* MCM ECC Error Generation Register */ 00643 00644 int32_t MCM_reserved10; 00645 00646 union { 00647 vuint32_t R; 00648 } FEAR; /* MCM Flash ECC Address Register */ 00649 00650 int16_t MCM_reserved11; 00651 00652 union { 00653 vuint8_t R; 00654 struct { 00655 vuint8_t:4; 00656 vuint8_t FEMR:4; 00657 } B; 00658 } FEMR; /* MCM Flash ECC Master Number Register */ 00659 00660 union { 00661 vuint8_t R; 00662 struct { 00663 vuint8_t WRITE:1; 00664 vuint8_t SIZE:3; 00665 vuint8_t PROTECTION:4; 00666 } B; 00667 } FEAT; /* MCM Flash ECC Attributes Register */ 00668 00669 int32_t MCM_reserved12; 00670 00671 union { 00672 vuint32_t R; 00673 } FEDR; /* MCM Flash ECC Data Register */ 00674 00675 union { 00676 vuint32_t R; 00677 } REAR; /* MCM RAM ECC Address Register */ 00678 00679 int8_t MCM_reserved13; 00680 00681 union { 00682 vuint8_t R; 00683 } RESR; /* MCM RAM ECC Address Register */ 00684 00685 union { 00686 vuint8_t R; 00687 struct { 00688 vuint8_t:4; 00689 vuint8_t REMR:4; 00690 } B; 00691 } REMR; /* MCM RAM ECC Master Number Register */ 00692 00693 union { 00694 vuint8_t R; 00695 struct { 00696 vuint8_t WRITE:1; 00697 vuint8_t SIZE:3; 00698 vuint8_t PROTECTION:4; 00699 } B; 00700 } REAT; /* MCM RAM ECC Attributes Register */ 00701 00702 int32_t MCM_reserved14; 00703 00704 union { 00705 vuint32_t R; 00706 } REDR; /* MCM RAM ECC Data Register */ 00707 00708 }; /* end of MCM_tag */ 00709 /****************************************************************************/ 00710 /* MODULE : RTC */ 00711 /****************************************************************************/ 00712 struct RTC_tag { 00713 union { 00714 vuint32_t R; 00715 struct { 00716 vuint32_t SUPV:1; 00717 vuint32_t:31; 00718 } B; 00719 } RTCSUPV; /* RTC Supervisor Control Register */ 00720 00721 union { 00722 vuint32_t R; 00723 struct { 00724 vuint32_t CNTEN:1; 00725 vuint32_t RTCIE:1; 00726 vuint32_t FRZEN:1; 00727 vuint32_t ROVREN:1; 00728 vuint32_t RTCVAL:12; 00729 vuint32_t APIEN:1; 00730 vuint32_t APIE:1; 00731 vuint32_t CLKSEL:2; 00732 vuint32_t DIV512EN:1; 00733 vuint32_t DIV32EN:1; 00734 vuint32_t APIVAL:10; 00735 } B; 00736 } RTCC; /* RTC Control Register */ 00737 00738 union { 00739 vuint32_t R; 00740 struct { 00741 vuint32_t:2; 00742 vuint32_t RTCF:1; 00743 vuint32_t:15; 00744 vuint32_t APIF:1; 00745 vuint32_t:2; 00746 vuint32_t ROVRF:1; 00747 vuint32_t:10; 00748 } B; 00749 } RTCS; /* RTC Status Register */ 00750 00751 union { 00752 vuint32_t R; 00753 struct { 00754 vuint32_t RTCCNT:32; 00755 } B; 00756 } RTCCNT; /* RTC Counter Register */ 00757 00758 }; /* end of RTC_tag */ 00759 /****************************************************************************/ 00760 /* MODULE : SIU */ 00761 /****************************************************************************/ 00762 struct SIU_tag { 00763 00764 int32_t SIU_reserved0; 00765 00766 union { /* MCU ID Register 1 */ 00767 vuint32_t R; 00768 struct { 00769 vuint32_t PARTNUM:16; 00770 vuint32_t CSP:1; 00771 vuint32_t PKG:5; 00772 vuint32_t:2; 00773 vuint32_t MAJORMASK:4; 00774 vuint32_t MINORMASK:4; 00775 } B; 00776 } MIDR; 00777 00778 union { /* MCU ID Register 2 */ 00779 vuint32_t R; 00780 struct { 00781 vuint32_t SF:1; 00782 vuint32_t FLASH_SIZE_1:4; 00783 vuint32_t FLASH_SIZE_2:4; 00784 vuint32_t:7; 00785 vuint32_t PARTNUM:8; 00786 vuint32_t:3; 00787 vuint32_t EE:1; 00788 vuint32_t:3; 00789 vuint32_t FR:1; 00790 } B; 00791 } MIDR2; 00792 00793 int32_t SIU_reserved1[2]; 00794 00795 union { /* Interrupt Status Flag Register */ 00796 vuint32_t R; 00797 struct { 00798 vuint32_t EIF31:1; 00799 vuint32_t EIF30:1; 00800 vuint32_t EIF29:1; 00801 vuint32_t EIF28:1; 00802 vuint32_t EIF27:1; 00803 vuint32_t EIF26:1; 00804 vuint32_t EIF25:1; 00805 vuint32_t EIF24:1; 00806 vuint32_t EIF23:1; 00807 vuint32_t EIF22:1; 00808 vuint32_t EIF21:1; 00809 vuint32_t EIF20:1; 00810 vuint32_t EIF19:1; 00811 vuint32_t EIF18:1; 00812 vuint32_t EIF17:1; 00813 vuint32_t EIF16:1; 00814 vuint32_t EIF15:1; 00815 vuint32_t EIF14:1; 00816 vuint32_t EIF13:1; 00817 vuint32_t EIF12:1; 00818 vuint32_t EIF11:1; 00819 vuint32_t EIF10:1; 00820 vuint32_t EIF9:1; 00821 vuint32_t EIF8:1; 00822 vuint32_t EIF7:1; 00823 vuint32_t EIF6:1; 00824 vuint32_t EIF5:1; 00825 vuint32_t EIF4:1; 00826 vuint32_t EIF3:1; 00827 vuint32_t EIF2:1; 00828 vuint32_t EIF1:1; 00829 vuint32_t EIF0:1; 00830 } B; 00831 } ISR; 00832 00833 union { /* Interrupt Request Enable Register */ 00834 vuint32_t R; 00835 struct { 00836 vuint32_t EIRE31:1; 00837 vuint32_t EIRE30:1; 00838 vuint32_t EIRE29:1; 00839 vuint32_t EIRE28:1; 00840 vuint32_t EIRE27:1; 00841 vuint32_t EIRE26:1; 00842 vuint32_t EIRE25:1; 00843 vuint32_t EIRE24:1; 00844 vuint32_t EIRE23:1; 00845 vuint32_t EIRE22:1; 00846 vuint32_t EIRE21:1; 00847 vuint32_t EIRE20:1; 00848 vuint32_t EIRE19:1; 00849 vuint32_t EIRE18:1; 00850 vuint32_t EIRE17:1; 00851 vuint32_t EIRE16:1; 00852 vuint32_t EIRE15:1; 00853 vuint32_t EIRE14:1; 00854 vuint32_t EIRE13:1; 00855 vuint32_t EIRE12:1; 00856 vuint32_t EIRE11:1; 00857 vuint32_t EIRE10:1; 00858 vuint32_t EIRE9:1; 00859 vuint32_t EIRE8:1; 00860 vuint32_t EIRE7:1; 00861 vuint32_t EIRE6:1; 00862 vuint32_t EIRE5:1; 00863 vuint32_t EIRE4:1; 00864 vuint32_t EIRE3:1; 00865 vuint32_t EIRE2:1; 00866 vuint32_t EIRE1:1; 00867 vuint32_t EIRE0:1; 00868 } B; 00869 } IRER; 00870 00871 int32_t SIU_reserved2[3]; 00872 00873 union { /* Interrupt Rising-Edge Event Enable Register */ 00874 vuint32_t R; 00875 struct { 00876 vuint32_t IREE31:1; 00877 vuint32_t IREE30:1; 00878 vuint32_t IREE29:1; 00879 vuint32_t IREE28:1; 00880 vuint32_t IREE27:1; 00881 vuint32_t IREE26:1; 00882 vuint32_t IREE25:1; 00883 vuint32_t IREE24:1; 00884 vuint32_t IREE23:1; 00885 vuint32_t IREE22:1; 00886 vuint32_t IREE21:1; 00887 vuint32_t IREE20:1; 00888 vuint32_t IREE19:1; 00889 vuint32_t IREE18:1; 00890 vuint32_t IREE17:1; 00891 vuint32_t IREE16:1; 00892 vuint32_t IREE15:1; 00893 vuint32_t IREE14:1; 00894 vuint32_t IREE13:1; 00895 vuint32_t IREE12:1; 00896 vuint32_t IREE11:1; 00897 vuint32_t IREE10:1; 00898 vuint32_t IREE9:1; 00899 vuint32_t IREE8:1; 00900 vuint32_t IREE7:1; 00901 vuint32_t IREE6:1; 00902 vuint32_t IREE5:1; 00903 vuint32_t IREE4:1; 00904 vuint32_t IREE3:1; 00905 vuint32_t IREE2:1; 00906 vuint32_t IREE1:1; 00907 vuint32_t IREE0:1; 00908 } B; 00909 } IREER; 00910 00911 union { /* Interrupt Falling-Edge Event Enable Register */ 00912 vuint32_t R; 00913 struct { 00914 vuint32_t IFEE31:1; 00915 vuint32_t IFEE30:1; 00916 vuint32_t IFEE29:1; 00917 vuint32_t IFEE28:1; 00918 vuint32_t IFEE27:1; 00919 vuint32_t IFEE26:1; 00920 vuint32_t IFEE25:1; 00921 vuint32_t IFEE24:1; 00922 vuint32_t IFEE23:1; 00923 vuint32_t IFEE22:1; 00924 vuint32_t IFEE21:1; 00925 vuint32_t IFEE20:1; 00926 vuint32_t IFEE19:1; 00927 vuint32_t IFEE18:1; 00928 vuint32_t IFEE17:1; 00929 vuint32_t IFEE16:1; 00930 vuint32_t IFEE15:1; 00931 vuint32_t IFEE14:1; 00932 vuint32_t IFEE13:1; 00933 vuint32_t IFEE12:1; 00934 vuint32_t IFEE11:1; 00935 vuint32_t IFEE10:1; 00936 vuint32_t IFEE9:1; 00937 vuint32_t IFEE8:1; 00938 vuint32_t IFEE7:1; 00939 vuint32_t IFEE6:1; 00940 vuint32_t IFEE5:1; 00941 vuint32_t IFEE4:1; 00942 vuint32_t IFEE3:1; 00943 vuint32_t IFEE2:1; 00944 vuint32_t IFEE1:1; 00945 vuint32_t IFEE0:1; 00946 } B; 00947 } IFEER; 00948 00949 union { /* Interrupt Filter Enable Register */ 00950 vuint32_t R; 00951 struct { 00952 vuint32_t IFE31:1; 00953 vuint32_t IFE30:1; 00954 vuint32_t IFE29:1; 00955 vuint32_t IFE28:1; 00956 vuint32_t IFE27:1; 00957 vuint32_t IFE26:1; 00958 vuint32_t IFE25:1; 00959 vuint32_t IFE24:1; 00960 vuint32_t IFE23:1; 00961 vuint32_t IFE22:1; 00962 vuint32_t IFE21:1; 00963 vuint32_t IFE20:1; 00964 vuint32_t IFE19:1; 00965 vuint32_t IFE18:1; 00966 vuint32_t IFE17:1; 00967 vuint32_t IFE16:1; 00968 vuint32_t IFE15:1; 00969 vuint32_t IFE14:1; 00970 vuint32_t IFE13:1; 00971 vuint32_t IFE12:1; 00972 vuint32_t IFE11:1; 00973 vuint32_t IFE10:1; 00974 vuint32_t IFE9:1; 00975 vuint32_t IFE8:1; 00976 vuint32_t IFE7:1; 00977 vuint32_t IFE6:1; 00978 vuint32_t IFE5:1; 00979 vuint32_t IFE4:1; 00980 vuint32_t IFE3:1; 00981 vuint32_t IFE2:1; 00982 vuint32_t IFE1:1; 00983 vuint32_t IFE0:1; 00984 } B; 00985 } IFER; 00986 00987 int32_t SIU_reserved3[3]; 00988 00989 union { /* Pad Configuration Registers */ 00990 vuint16_t R; 00991 struct { 00992 vuint16_t:1; 00993 vuint16_t SME:1; 00994 vuint16_t APC:1; 00995 vuint16_t:1; 00996 vuint16_t PA:2; 00997 vuint16_t OBE:1; 00998 vuint16_t IBE:1; 00999 vuint16_t DCS:2; 01000 vuint16_t ODE:1; 01001 vuint16_t HYS:1; 01002 vuint16_t SRC:2; 01003 vuint16_t WPE:1; 01004 vuint16_t WPS:1; 01005 } B; 01006 } PCR[512]; 01007 01008 int32_t SIU_reserved4[48]; /* {0x500-0x440}/0x4 */ 01009 01010 union { /* Pad Selection for Multiplexed Input Register */ 01011 vuint8_t R; 01012 struct { 01013 vuint8_t:4; 01014 vuint8_t PADSEL:4; 01015 } B; 01016 } PSMI[256]; 01017 01018 union { /* GPIO Pin Data Output Registers */ 01019 vuint8_t R; 01020 struct { 01021 vuint8_t:7; 01022 vuint8_t PDO:1; 01023 } B; 01024 } GPDO[512]; 01025 01026 union { /* GPIO Pin Data Input Registers */ 01027 vuint8_t R; 01028 struct { 01029 vuint8_t:7; 01030 vuint8_t PDI:1; 01031 } B; 01032 } GPDI[512]; 01033 01034 int32_t SIU_reserved5[128]; /* {0xC00-0xA00}/0x4 */ 01035 01036 union { /* Parallel GPIO Pin Data Output Register */ 01037 vuint32_t R; 01038 struct { 01039 vuint32_t PPD0:32; 01040 } B; 01041 } PGPDO[16]; 01042 01043 union { /* Parallel GPIO Pin Data Input Register */ 01044 vuint32_t R; 01045 struct { 01046 vuint32_t PPDI:32; 01047 } B; 01048 } PGPDI[16]; 01049 01050 union { /* Masked Parallel GPIO Pin Data Out Register */ 01051 vuint32_t R; 01052 struct { 01053 vuint32_t MASK:16; 01054 vuint32_t MPPDO:16; 01055 } B; 01056 } MPGPDO[32]; 01057 01058 int32_t SIU_reserved6[192]; /* {0x1000-0x0D00}/0x4 */ 01059 01060 union { /* Interrupt Filter Maximum Counter Register */ 01061 vuint32_t R; 01062 struct { 01063 vuint32_t:28; 01064 vuint32_t MAXCNT:4; 01065 } B; 01066 } IFMC[32]; 01067 01068 union { /* Interrupt Filter Clock Prescaler Register */ 01069 vuint32_t R; 01070 struct { 01071 vuint32_t:28; 01072 vuint32_t IFCP:4; 01073 } B; 01074 } IFCPR; 01075 01076 }; /* end of SIU_tag */ 01077 /****************************************************************************/ 01078 /* MODULE : SSCM */ 01079 /****************************************************************************/ 01080 struct SSCM_tag { 01081 union { 01082 vuint16_t R; 01083 struct { 01084 vuint16_t:4; 01085 vuint16_t NXEN:1; 01086 vuint16_t:1; 01087 vuint16_t SEC:1; 01088 vuint16_t:1; 01089 vuint16_t BMODE:3; 01090 vuint16_t DMID:1; 01091 vuint16_t ABD:1; 01092 vuint16_t:3; 01093 } B; 01094 } STATUS; /* Status Register */ 01095 01096 union { 01097 vuint16_t R; 01098 struct { 01099 vuint16_t SRAMSIZE:5; 01100 vuint16_t IFLASHSIZE:5; 01101 vuint16_t IVLD:1; 01102 vuint16_t DFLASHSIZE:4; 01103 vuint16_t DVLD:1; 01104 } B; 01105 } MEMCONFIG; /* System Memory Configuration Register */ 01106 01107 int16_t SSCM_reserved; 01108 01109 union { 01110 vuint16_t R; 01111 struct { 01112 vuint16_t:14; 01113 vuint16_t PAE:1; 01114 vuint16_t RAE:1; 01115 } B; 01116 } ERROR; /* Error Configuration Register */ 01117 01118 union { 01119 vuint16_t R; 01120 struct { 01121 vuint16_t:13; 01122 vuint16_t DEBUG_MODE:3; 01123 } B; 01124 } DEBUGPORT; /* Debug Status Port Register */ 01125 01126 int16_t SSCM_reserved1; 01127 01128 union { 01129 vuint32_t R; 01130 struct { 01131 vuint32_t PWD_HI:32; 01132 } B; 01133 } PWCMPH; /* Password Comparison Register High Word */ 01134 01135 union { 01136 vuint32_t R; 01137 struct { 01138 vuint32_t PWD_LO:32; 01139 } B; 01140 } PWCMPL; /* Password Comparison Register Low Word */ 01141 01142 }; /* end of SSCM_tag */ 01143 /****************************************************************************/ 01144 /* MODULE : STM */ 01145 /****************************************************************************/ 01146 struct STM_tag { 01147 01148 union { 01149 vuint32_t R; 01150 struct { 01151 vuint32_t:16; 01152 vuint32_t CPS:8; 01153 vuint32_t:6; 01154 vuint32_t FRZ:1; 01155 vuint32_t TEN:1; 01156 } B; 01157 } CR0; /* STM Control Register */ 01158 01159 union { 01160 vuint32_t R; 01161 } CNT0; /* STM Count Register */ 01162 01163 int32_t STM_reserved[2]; 01164 01165 union { 01166 vuint32_t R; 01167 struct { 01168 vuint32_t:31; 01169 vuint32_t CEN:1; 01170 } B; 01171 } CCR0; /* STM Channel Control Register 0 */ 01172 01173 union { 01174 vuint32_t R; 01175 struct { 01176 vuint32_t:31; 01177 vuint32_t CIF:1; 01178 } B; 01179 } CIR0; /* STM Channel Interrupt Register 0 */ 01180 01181 union { 01182 vuint32_t R; 01183 } CMP0; /* STM Channel Compare Register 0 */ 01184 01185 int32_t STM_reserved1; 01186 01187 union { 01188 vuint32_t R; 01189 struct { 01190 vuint32_t:31; 01191 vuint32_t CEN:1; 01192 } B; 01193 } CCR1; /* STM Channel Control Register 1 */ 01194 01195 union { 01196 vuint32_t R; 01197 struct { 01198 vuint32_t:31; 01199 vuint32_t CIF:1; 01200 } B; 01201 } CIR1; /* STM Channel Interrupt Register 1 */ 01202 01203 union { 01204 vuint32_t R; 01205 } CMP1; /* STM Channel Compare Register 1 */ 01206 01207 int32_t STM_reserved2; 01208 01209 union { 01210 vuint32_t R; 01211 struct { 01212 vuint32_t:31; 01213 vuint32_t CEN:1; 01214 } B; 01215 } CCR2; /* STM Channel Control Register 2 */ 01216 01217 union { 01218 vuint32_t R; 01219 struct { 01220 vuint32_t:31; 01221 vuint32_t CIF:1; 01222 } B; 01223 } CIR2; /* STM Channel Interrupt Register 2 */ 01224 01225 union { 01226 vuint32_t R; 01227 } CMP2; /* STM Channel Compare Register 2 */ 01228 01229 int32_t STM_reserved3; 01230 01231 union { 01232 vuint32_t R; 01233 struct { 01234 vuint32_t:31; 01235 vuint32_t CEN:1; 01236 } B; 01237 } CCR3; /* STM Channel Control Register 3 */ 01238 01239 union { 01240 vuint32_t R; 01241 struct { 01242 vuint32_t:31; 01243 vuint32_t CIF:1; 01244 } B; 01245 } CIR3; /* STM Channel Interrupt Register 3 */ 01246 01247 union { 01248 vuint32_t R; 01249 } CMP3; /* STM Channel Compare Register 3 */ 01250 01251 }; /* end of STM_tag */ 01252 /****************************************************************************/ 01253 /* MODULE : SWT */ 01254 /****************************************************************************/ 01255 struct SWT_tag { 01256 union { 01257 vuint32_t R; 01258 struct { 01259 vuint32_t MAP0:1; 01260 vuint32_t MAP1:1; 01261 vuint32_t MAP2:1; 01262 vuint32_t MAP3:1; 01263 vuint32_t MAP4:1; 01264 vuint32_t MAP5:1; 01265 vuint32_t MAP6:1; 01266 vuint32_t MAP7:1; 01267 vuint32_t:15; 01268 vuint32_t RIA:1; 01269 vuint32_t WND:1; 01270 vuint32_t ITR:1; 01271 vuint32_t HLK:1; 01272 vuint32_t SLK:1; 01273 vuint32_t CSL:1; 01274 vuint32_t STP:1; 01275 vuint32_t FRZ:1; 01276 vuint32_t WEN:1; 01277 } B; 01278 } CR; /* SWT Control Register */ 01279 01280 union { 01281 vuint32_t R; 01282 struct { 01283 vuint32_t:31; 01284 vuint32_t TIF:1; 01285 } B; 01286 } IR; /* SWT Interrupt Register */ 01287 01288 union { 01289 vuint32_t R; 01290 struct { 01291 vuint32_t WTO:32; 01292 } B; 01293 } TO; /* SWT Time-Out Register */ 01294 01295 union { 01296 vuint32_t R; 01297 struct { 01298 vuint32_t WST:32; 01299 } B; 01300 } WN; /* SWT Window Register */ 01301 01302 union { 01303 vuint32_t R; 01304 struct { 01305 vuint32_t:16; 01306 vuint32_t WSC:16; 01307 } B; 01308 } SR; /* SWT Service Register */ 01309 01310 union { 01311 vuint32_t R; 01312 struct { 01313 vuint32_t CNT:32; 01314 } B; 01315 } CO; /* SWT Counter Output Register */ 01316 01317 }; /* end of SWT_tag */ 01318 /****************************************************************************/ 01319 /* MODULE : WKUP */ 01320 /****************************************************************************/ 01321 struct WKUP_tag { 01322 union { 01323 vuint32_t R; 01324 struct { 01325 vuint32_t NIF0:1; 01326 vuint32_t NOVF0:1; 01327 vuint32_t:6; 01328 vuint32_t NIF1:1; 01329 vuint32_t NOVF1:1; 01330 vuint32_t:6; 01331 vuint32_t NIF2:1; 01332 vuint32_t NOVF2:1; 01333 vuint32_t:6; 01334 vuint32_t NIF3:1; 01335 vuint32_t NOVF3:1; 01336 vuint32_t:6; 01337 } B; 01338 } NSR; /* NMI Status Register */ 01339 01340 int32_t WKUP_reserved; 01341 01342 union { 01343 vuint32_t R; 01344 struct { 01345 vuint32_t NLOCK0:1; 01346 vuint32_t NDSS0:2; 01347 vuint32_t NWRE0:1; 01348 vuint32_t:1; 01349 vuint32_t NREE0:1; 01350 vuint32_t NFEE0:1; 01351 vuint32_t NFE0:1; 01352 vuint32_t NLOCK1:1; 01353 vuint32_t NDSS1:2; 01354 vuint32_t NWRE1:1; 01355 vuint32_t:1; 01356 vuint32_t NREE1:1; 01357 vuint32_t NFEE1:1; 01358 vuint32_t NFE1:1; 01359 vuint32_t NLOCK2:1; 01360 vuint32_t NDSS2:2; 01361 vuint32_t NWRE2:1; 01362 vuint32_t:1; 01363 vuint32_t NREE2:1; 01364 vuint32_t NFEE2:1; 01365 vuint32_t NFE2:1; 01366 vuint32_t NLOCK3:1; 01367 vuint32_t NDSS3:2; 01368 vuint32_t NWRE3:1; 01369 vuint32_t:1; 01370 vuint32_t NREE3:1; 01371 vuint32_t NFEE3:1; 01372 vuint32_t NFE3:1; 01373 } B; 01374 } NCR; /* NMI Configuration Register */ 01375 01376 int32_t WKUP_reserved1[2]; 01377 01378 union { 01379 vuint32_t R; 01380 struct { 01381 vuint32_t EIF:32; 01382 } B; 01383 } WISR; /* Wakeup/Interrupt Status Flag Register */ 01384 01385 union { 01386 vuint32_t R; 01387 struct { 01388 vuint32_t EIRE:32; 01389 } B; 01390 } IRER; /* Interrupt Request Enable Register */ 01391 01392 union { 01393 vuint32_t R; 01394 struct { 01395 vuint32_t WRE:32; 01396 } B; 01397 } WRER; /* Wakeup Request Enable Register */ 01398 01399 int32_t WKUP_reserved2[2]; 01400 01401 union { 01402 vuint32_t R; 01403 struct { 01404 vuint32_t IREE:32; 01405 } B; 01406 } WIREER; /* Wakeup/Interrupt Rising-Edge Event Enable Register */ 01407 01408 union { 01409 vuint32_t R; 01410 struct { 01411 vuint32_t IFEE:32; 01412 } B; 01413 } WIFEER; /* Wakeup/Interrupt Falling-Edge Event Enable Register */ 01414 01415 union { 01416 vuint32_t R; 01417 struct { 01418 vuint32_t IFE:32; 01419 } B; 01420 } WIFER; /* Wakeup/Interrupt Filter Enable Register */ 01421 01422 union { 01423 vuint32_t R; 01424 struct { 01425 vuint32_t IPUE:32; 01426 } B; 01427 } WIPUER; /* Wakeup/Interrupt Pullup Enable Register */ 01428 01429 }; /* end of WKUP_tag */ 01430 /****************************************************************************/ 01431 /* MODULE : LINFLEX */ 01432 /****************************************************************************/ 01433 01434 struct LINFLEX_tag { 01435 01436 int16_t LINFLEX_reserved1; 01437 01438 union { 01439 vuint16_t R; 01440 struct { 01441 vuint16_t CCD:1; 01442 vuint16_t CFD:1; 01443 vuint16_t LASE:1; 01444 vuint16_t AWUM:1; // LCH vuint16_t AUTOWU:1; 01445 vuint16_t MBL:4; 01446 vuint16_t BF:1; 01447 vuint16_t SFTM:1; 01448 vuint16_t LBKM:1; 01449 vuint16_t MME:1; 01450 vuint16_t SBDT:1; // LCH vuint16_t SSBL:1; 01451 vuint16_t RBLM:1; 01452 vuint16_t SLEEP:1; 01453 vuint16_t INIT:1; 01454 } B; 01455 } LINCR1; /* LINFLEX LIN Control Register 1 */ 01456 01457 int16_t LINFLEX_reserved2; 01458 01459 union { 01460 vuint16_t R; 01461 struct { 01462 vuint16_t SZIE:1; 01463 vuint16_t OCIE:1; 01464 vuint16_t BEIE:1; 01465 vuint16_t CEIE:1; 01466 vuint16_t HEIE:1; 01467 vuint16_t:2; 01468 vuint16_t FEIE:1; 01469 vuint16_t BOIE:1; 01470 vuint16_t LSIE:1; 01471 vuint16_t WUIE:1; 01472 vuint16_t DBFIE:1; 01473 vuint16_t DBEIE:1; 01474 vuint16_t DRIE:1; 01475 vuint16_t DTIE:1; 01476 vuint16_t HRIE:1; 01477 } B; 01478 } LINIER; /* LINFLEX LIN Interrupt Enable Register */ 01479 01480 int16_t LINFLEX_reserved3; 01481 01482 union { 01483 vuint16_t R; 01484 struct { 01485 vuint16_t LINS:4; 01486 vuint16_t:2; 01487 vuint16_t RMB:1; 01488 vuint16_t:1; 01489 vuint16_t RBSY:1; // LCH vuint16_t RXBUSY:1; 01490 vuint16_t RPS:1; // LCH vuint16_t RDI:1; 01491 vuint16_t WUF:1; 01492 vuint16_t DBFF:1; 01493 vuint16_t DBEF:1; 01494 vuint16_t DRF:1; 01495 vuint16_t DTF:1; 01496 vuint16_t HRF:1; 01497 } B; 01498 } LINSR; /* LINFLEX LIN Status Register */ 01499 01500 int16_t LINFLEX_reserved4; 01501 01502 union { 01503 vuint16_t R; 01504 struct { 01505 vuint16_t SZF:1; 01506 vuint16_t OCF:1; 01507 vuint16_t BEF:1; 01508 vuint16_t CEF:1; 01509 vuint16_t SFEF:1; 01510 vuint16_t BDEF:1; 01511 vuint16_t IDPEF:1; 01512 vuint16_t FEF:1; 01513 vuint16_t BOF:1; 01514 vuint16_t:6; 01515 vuint16_t NF:1; 01516 } B; 01517 } LINESR; /* LINFLEX LIN Error Status Register */ 01518 01519 int16_t LINFLEX_reserved5; 01520 01521 union { 01522 vuint16_t R; 01523 struct { 01524 vuint16_t:1; 01525 vuint16_t TDFL:2; 01526 vuint16_t:1; 01527 vuint16_t RDFL:2; 01528 vuint16_t:4; 01529 vuint16_t RXEN:1; 01530 vuint16_t TXEN:1; 01531 vuint16_t OP:1; //LCH vuint16_t PARITYODD:1; 01532 vuint16_t PCE:1; 01533 vuint16_t WL:1; 01534 vuint16_t UART:1; 01535 } B; 01536 } UARTCR; /* LINFLEX UART Mode Control Register */ 01537 01538 int16_t LINFLEX_reserved6; 01539 01540 union { 01541 vuint16_t R; 01542 struct { 01543 vuint16_t SZF:1; 01544 vuint16_t OCF:1; 01545 vuint16_t PE:4; 01546 vuint16_t RMB:1; 01547 vuint16_t FEF:1; 01548 vuint16_t BOF:1; 01549 vuint16_t RPS:1; // LCH vuint16_t RDI:1; 01550 vuint16_t WUF:1; 01551 vuint16_t:2; 01552 vuint16_t DRF:1; 01553 vuint16_t DTF:1; 01554 vuint16_t NF:1; 01555 } B; 01556 } UARTSR; /* LINFLEX UART Mode Status Register */ 01557 01558 int16_t LINFLEX_reserved7; 01559 01560 union { 01561 vuint16_t R; 01562 struct { 01563 vuint16_t:5; 01564 vuint16_t LTOM:1; //LCH vuint16_t MODE:1; 01565 vuint16_t IOT:1; 01566 vuint16_t TOCE:1; 01567 vuint16_t CNT:8; 01568 } B; 01569 } LINTCSR; /* LINFLEX LIN Time-Out Control Status Register */ 01570 01571 int16_t LINFLEX_reserved8; 01572 01573 union { 01574 vuint16_t R; 01575 struct { 01576 vuint16_t OC2:8; 01577 vuint16_t OC1:8; 01578 } B; 01579 } LINOCR; /* LINFLEX LIN Output Compare Register */ 01580 01581 int16_t LINFLEX_reserved9; 01582 01583 union { 01584 vuint16_t R; 01585 struct { 01586 vuint16_t:4; 01587 vuint16_t RTO:4; // LCH vuint16_t RTC:4; 01588 vuint16_t:1; 01589 vuint16_t HTO:7; // LCH vuint16_t HTC:7; 01590 } B; 01591 } LINTOCR; /* LINFLEX LIN Output Compare Register */ 01592 01593 int16_t LINFLEX_reserved10; 01594 01595 union { 01596 vuint16_t R; 01597 struct { 01598 vuint16_t:12; 01599 vuint16_t DIV_F:4; // LCH vuint16_t FBR:4; 01600 } B; 01601 } LINFBRR; /* LINFLEX LIN Fractional Baud Rate Register */ 01602 01603 int16_t LINFLEX_reserved11; 01604 01605 union { 01606 vuint16_t R; 01607 struct { 01608 vuint16_t:3; 01609 vuint16_t DIV_M:13; // LCH vuint16_t IBR:13; 01610 } B; 01611 } LINIBRR; /* LINFLEX LIN Integer Baud Rate Register */ 01612 01613 int16_t LINFLEX_reserved12; 01614 01615 union { 01616 vuint16_t R; 01617 struct { 01618 vuint16_t:8; 01619 vuint16_t CF:8; 01620 } B; 01621 } LINCFR; /* LINFLEX LIN Checksum Field Register */ 01622 01623 int16_t LINFLEX_reserved13; 01624 01625 union { 01626 vuint16_t R; 01627 struct { 01628 vuint16_t:1; 01629 vuint16_t IOBE:1; 01630 vuint16_t IOPE:1; 01631 vuint16_t WURQ:1; 01632 vuint16_t DDRQ:1; 01633 vuint16_t DTRQ:1; 01634 vuint16_t ABRQ:1; 01635 vuint16_t HTRQ:1; 01636 vuint16_t:8; 01637 } B; 01638 } LINCR2; /* LINFLEX LIN Control Register 2 */ 01639 01640 int16_t LINFLEX_reserved14; 01641 01642 union { 01643 vuint16_t R; 01644 struct { 01645 vuint16_t DFL:6; 01646 vuint16_t DIR:1; 01647 vuint16_t CCS:1; 01648 vuint16_t:2; // LCH vuint16_t:1; 01649 vuint16_t ID:6; 01650 } B; 01651 } BIDR; /* LINFLEX Buffer Identifier Register */ 01652 01653 union { 01654 vuint32_t R; 01655 struct { 01656 vuint32_t DATA3:8; 01657 vuint32_t DATA2:8; 01658 vuint32_t DATA1:8; 01659 vuint32_t DATA0:8; 01660 } B; 01661 } BDRL; /* LINFLEX Buffer Data Register Least Significant */ 01662 01663 union { 01664 vuint32_t R; 01665 struct { 01666 vuint32_t DATA7:8; 01667 vuint32_t DATA6:8; 01668 vuint32_t DATA5:8; 01669 vuint32_t DATA4:8; 01670 } B; 01671 } BDRM; /* LINFLEX Buffer Data Register Most Significant */ 01672 01673 int16_t LINFLEX_reserved15; 01674 01675 union { 01676 vuint16_t R; 01677 struct { 01678 vuint16_t:8; 01679 vuint16_t FACT:8; 01680 } B; 01681 } IFER; /* LINFLEX Identifier Filter Enable Register */ 01682 01683 int16_t LINFLEX_reserved16; 01684 01685 union { 01686 vuint16_t R; 01687 struct { 01688 vuint16_t:12; 01689 vuint16_t IFMI:4; 01690 } B; 01691 } IFMI; /* LINFLEX Identifier Filter Match Index Register */ 01692 01693 int16_t LINFLEX_reserved17; 01694 01695 union { 01696 vuint16_t R; 01697 struct { 01698 vuint16_t:12; 01699 vuint16_t IFM:4; 01700 } B; 01701 } IFMR; /* LINFLEX Identifier Filter Mode Register */ 01702 01703 int16_t LINFLEX_reserved18; 01704 01705 union { 01706 vuint16_t R; 01707 struct { 01708 vuint16_t:3; 01709 vuint16_t DFL:3; 01710 vuint16_t DIR:1; 01711 vuint16_t CCS:1; 01712 vuint16_t:2; 01713 vuint16_t ID:6; 01714 } B; 01715 } IFCR0; /* LINFLEX Identifier Filter Control Register 0 */ 01716 01717 int16_t LINFLEX_reserved19; 01718 01719 union { 01720 vuint16_t R; 01721 struct { 01722 vuint16_t:3; 01723 vuint16_t DFL:3; 01724 vuint16_t DIR:1; 01725 vuint16_t CCS:1; 01726 vuint16_t:2; 01727 vuint16_t ID:6; 01728 } B; 01729 } IFCR1; /* LINFLEX Identifier Filter Control Register 1 */ 01730 01731 int16_t LINFLEX_reserved20; 01732 01733 union { 01734 vuint16_t R; 01735 struct { 01736 vuint16_t:3; 01737 vuint16_t DFL:3; 01738 vuint16_t DIR:1; 01739 vuint16_t CCS:1; 01740 vuint16_t:2; 01741 vuint16_t ID:6; 01742 } B; 01743 } IFCR2; /* LINFLEX Identifier Filter Control Register 2 */ 01744 01745 int16_t LINFLEX_reserved21; 01746 01747 union { 01748 vuint16_t R; 01749 struct { 01750 vuint16_t:3; 01751 vuint16_t DFL:3; 01752 vuint16_t DIR:1; 01753 vuint16_t CCS:1; 01754 vuint16_t:2; 01755 vuint16_t ID:6; 01756 } B; 01757 } IFCR3; /* LINFLEX Identifier Filter Control Register 3 */ 01758 01759 int16_t LINFLEX_reserved22; 01760 01761 union { 01762 vuint16_t R; 01763 struct { 01764 vuint16_t:3; 01765 vuint16_t DFL:3; 01766 vuint16_t DIR:1; 01767 vuint16_t CCS:1; 01768 vuint16_t:2; 01769 vuint16_t ID:6; 01770 } B; 01771 } IFCR4; /* LINFLEX Identifier Filter Control Register 4 */ 01772 01773 int16_t LINFLEX_reserved23; 01774 01775 union { 01776 vuint16_t R; 01777 struct { 01778 vuint16_t:3; 01779 vuint16_t DFL:3; 01780 vuint16_t DIR:1; 01781 vuint16_t CCS:1; 01782 vuint16_t:2; 01783 vuint16_t ID:6; 01784 } B; 01785 } IFCR5; /* LINFLEX Identifier Filter Control Register 5 */ 01786 01787 int16_t LINFLEX_reserved24; 01788 01789 union { 01790 vuint16_t R; 01791 struct { 01792 vuint16_t:3; 01793 vuint16_t DFL:3; 01794 vuint16_t DIR:1; 01795 vuint16_t CCS:1; 01796 vuint16_t:2; 01797 vuint16_t ID:6; 01798 } B; 01799 } IFCR6; /* LINFLEX Identifier Filter Control Register 6 */ 01800 01801 int16_t LINFLEX_reserved25; 01802 01803 union { 01804 vuint16_t R; 01805 struct { 01806 vuint16_t:3; 01807 vuint16_t DFL:3; 01808 vuint16_t DIR:1; 01809 vuint16_t CCS:1; 01810 vuint16_t:2; 01811 vuint16_t ID:6; 01812 } B; 01813 } IFCR7; /* LINFLEX Identifier Filter Control Register 7 */ 01814 01815 }; /* end of LINFLEX_tag */ 01816 /****************************************************************************/ 01817 /* MODULE : ME */ 01818 /****************************************************************************/ 01819 struct ME_tag { 01820 01821 union { 01822 vuint32_t R; 01823 struct { 01824 vuint32_t S_CURRENTMODE:4; 01825 vuint32_t S_MTRANS:1; 01826 vuint32_t S_DC:1; 01827 vuint32_t:2; 01828 vuint32_t S_PDO:1; 01829 vuint32_t:2; 01830 vuint32_t S_MVR:1; 01831 vuint32_t S_DFLA:2; 01832 vuint32_t S_CFLA:2; 01833 vuint32_t:8; 01834 vuint32_t S_PLL1:1; 01835 vuint32_t S_PLL0:1; 01836 vuint32_t S_OSC:1; 01837 vuint32_t S_RC:1; 01838 vuint32_t S_SYSCLK:4; 01839 } B; 01840 } GS; /* Global Status Register */ 01841 01842 union { 01843 vuint32_t R; 01844 struct { 01845 vuint32_t TARGET_MODE:4; 01846 vuint32_t:12; 01847 vuint32_t KEY:16; 01848 } B; 01849 } MCTL; /* Mode Control Register */ 01850 01851 union { 01852 vuint32_t R; 01853 struct { 01854 vuint32_t:18; 01855 vuint32_t STANDBY0:1; 01856 vuint32_t:2; 01857 vuint32_t STOP0:1; 01858 vuint32_t:1; 01859 vuint32_t HALT0:1; 01860 vuint32_t RUN3:1; 01861 vuint32_t RUN2:1; 01862 vuint32_t RUN1:1; 01863 vuint32_t RUN0:1; 01864 vuint32_t DRUN:1; 01865 vuint32_t SAFE:1; 01866 vuint32_t TEST:1; 01867 vuint32_t RESET:1; 01868 } B; 01869 } MER; /* Mode Enable Register */ 01870 01871 union { 01872 vuint32_t R; 01873 struct { 01874 vuint32_t:28; 01875 vuint32_t I_CONF:1; 01876 vuint32_t I_MODE:1; 01877 vuint32_t I_AFE:1; 01878 vuint32_t I_TC:1; 01879 } B; 01880 } IS; /* Interrupt Status Register */ 01881 01882 union { 01883 vuint32_t R; 01884 struct { 01885 vuint32_t:28; 01886 vuint32_t M_CONF:1; 01887 vuint32_t M_MODE:1; 01888 vuint32_t M_AFE:1; 01889 vuint32_t M_TC:1; 01890 } B; 01891 } IM; /* Interrupt Mask Register */ 01892 01893 union { 01894 vuint32_t R; 01895 struct { 01896 vuint32_t:27; 01897 vuint32_t S_MTI:1; 01898 vuint32_t S_MRI:1; 01899 vuint32_t S_DMA:1; 01900 vuint32_t S_NMA:1; 01901 vuint32_t S_SEA:1; 01902 } B; 01903 } IMTS; /* Invalid Mode Transition Status Register */ 01904 01905 int32_t ME_reserved0[2]; 01906 01907 union { 01908 vuint32_t R; 01909 struct { 01910 vuint32_t:8; 01911 vuint32_t PDO:1; 01912 vuint32_t:2; 01913 vuint32_t MVRON:1; 01914 vuint32_t DFLAON:2; 01915 vuint32_t CFLAON:2; 01916 vuint32_t:8; 01917 vuint32_t PLL2ON:1; 01918 vuint32_t PLL1ON:1; 01919 vuint32_t XOSC0ON:1; 01920 vuint32_t IRCON:1; 01921 vuint32_t SYSCLK:4; 01922 } B; 01923 } RESET; /* Reset Mode Configuration Register */ 01924 01925 union { 01926 vuint32_t R; 01927 struct { 01928 vuint32_t:8; 01929 vuint32_t PDO:1; 01930 vuint32_t:2; 01931 vuint32_t MVRON:1; 01932 vuint32_t DFLAON:2; 01933 vuint32_t CFLAON:2; 01934 vuint32_t:8; 01935 vuint32_t PLL2ON:1; 01936 vuint32_t PLL1ON:1; 01937 vuint32_t XOSC0ON:1; 01938 vuint32_t IRCON:1; 01939 vuint32_t SYSCLK:4; 01940 } B; 01941 } TEST; /* Test Mode Configuration Register */ 01942 01943 union { 01944 vuint32_t R; 01945 struct { 01946 vuint32_t:8; 01947 vuint32_t PDO:1; 01948 vuint32_t:2; 01949 vuint32_t MVRON:1; 01950 vuint32_t DFLAON:2; 01951 vuint32_t CFLAON:2; 01952 vuint32_t:8; 01953 vuint32_t PLL2ON:1; 01954 vuint32_t PLL1ON:1; 01955 vuint32_t XOSC0ON:1; 01956 vuint32_t IRCON:1; 01957 vuint32_t SYSCLK:4; 01958 } B; 01959 } SAFE; /* Safe Mode Configuration Register */ 01960 01961 union { 01962 vuint32_t R; 01963 struct { 01964 vuint32_t:8; 01965 vuint32_t PDO:1; 01966 vuint32_t:2; 01967 vuint32_t MVRON:1; 01968 vuint32_t DFLAON:2; 01969 vuint32_t CFLAON:2; 01970 vuint32_t:8; 01971 vuint32_t PLL2ON:1; 01972 vuint32_t PLL1ON:1; 01973 vuint32_t XOSC0ON:1; 01974 vuint32_t IRCON:1; 01975 vuint32_t SYSCLK:4; 01976 } B; 01977 } DRUN; /* DRUN Mode Configuration Register */ 01978 01979 union { 01980 vuint32_t R; 01981 struct { 01982 vuint32_t:8; 01983 vuint32_t PDO:1; 01984 vuint32_t:2; 01985 vuint32_t MVRON:1; 01986 vuint32_t DFLAON:2; 01987 vuint32_t CFLAON:2; 01988 vuint32_t:8; 01989 vuint32_t PLL2ON:1; 01990 vuint32_t PLL1ON:1; 01991 vuint32_t XOSC0ON:1; 01992 vuint32_t IRCON:1; 01993 vuint32_t SYSCLK:4; 01994 } B; 01995 } RUN[4]; /* RUN 0->4 Mode Configuration Register */ 01996 01997 union { 01998 vuint32_t R; 01999 struct { 02000 vuint32_t:8; 02001 vuint32_t PDO:1; 02002 vuint32_t:2; 02003 vuint32_t MVRON:1; 02004 vuint32_t DFLAON:2; 02005 vuint32_t CFLAON:2; 02006 vuint32_t:8; 02007 vuint32_t PLL2ON:1; 02008 vuint32_t PLL1ON:1; 02009 vuint32_t XOSC0ON:1; 02010 vuint32_t IRCON:1; 02011 vuint32_t SYSCLK:4; 02012 } B; 02013 } HALT0; /* HALT0 Mode Configuration Register */ 02014 02015 int32_t ME_reserved1; 02016 02017 union { 02018 vuint32_t R; 02019 struct { 02020 vuint32_t:8; 02021 vuint32_t PDO:1; 02022 vuint32_t:2; 02023 vuint32_t MVRON:1; 02024 vuint32_t DFLAON:2; 02025 vuint32_t CFLAON:2; 02026 vuint32_t:8; 02027 vuint32_t PLL2ON:1; 02028 vuint32_t PLL1ON:1; 02029 vuint32_t XOSC0ON:1; 02030 vuint32_t IRCON:1; 02031 vuint32_t SYSCLK:4; 02032 } B; 02033 } STOP0; /* STOP0 Mode Configuration Register */ 02034 02035 int32_t ME_reserved2[2]; 02036 02037 union { 02038 vuint32_t R; 02039 struct { 02040 vuint32_t:8; 02041 vuint32_t PDO:1; 02042 vuint32_t:2; 02043 vuint32_t MVRON:1; 02044 vuint32_t DFLAON:2; 02045 vuint32_t CFLAON:2; 02046 vuint32_t:8; 02047 vuint32_t PLL2ON:1; 02048 vuint32_t PLL1ON:1; 02049 vuint32_t XOSC0ON:1; 02050 vuint32_t IRCON:1; 02051 vuint32_t SYSCLK:4; 02052 } B; 02053 } STANDBY0; /* STANDBY0 Mode Configuration Register */ 02054 02055 int32_t ME_reserved3[2]; 02056 02057 union { 02058 vuint32_t R; 02059 struct { 02060 vuint32_t PERIPH:32; 02061 } B; 02062 } PS[4]; /* Peripheral Status 0->4 Register */ 02063 02064 int32_t ME_reserved4[4]; 02065 02066 union { 02067 vuint32_t R; 02068 struct { 02069 vuint32_t:24; 02070 vuint32_t RUN3:1; 02071 vuint32_t RUN2:1; 02072 vuint32_t RUN1:1; 02073 vuint32_t RUN0:1; 02074 vuint32_t DRUN:1; 02075 vuint32_t SAFE:1; 02076 vuint32_t TEST:1; 02077 vuint32_t RESET:1; 02078 } B; 02079 } RUNPC[8]; /* RUN Peripheral Configuration 0->7 Register */ 02080 02081 union { 02082 vuint32_t R; 02083 struct { 02084 vuint32_t:18; 02085 vuint32_t STANDBY0:1; 02086 vuint32_t:2; 02087 vuint32_t STOP0:1; 02088 vuint32_t:1; 02089 vuint32_t HALT0:1; 02090 vuint32_t:8; 02091 } B; 02092 } LPPC[8]; /* Low Power Peripheral Configuration 0->7 Register */ 02093 02094 union { 02095 vuint8_t R; 02096 struct { 02097 vuint8_t:1; 02098 vuint8_t DBG_F:1; 02099 vuint8_t LP_CFG:3; 02100 vuint8_t RUN_CFG:3; 02101 } B; 02102 } PCTL[144]; /* Peripheral Control 0->143 Register */ 02103 02104 }; /* end of ME_tag */ 02105 /****************************************************************************/ 02106 /* MODULE : CGM */ 02107 /****************************************************************************/ 02108 struct CGM_tag { 02109 02110 /* The CGM provides a unified register interface, enabling access to 02111 all clock sources: 02112 02113 Clock Type | Starting Address Map | Associated Clock Sources 02114 ------------------------------------------------------------ 02115 System | C3FE0000 | OSC_CTL 02116 " | - | Reserved 02117 " | C3FE0040 | LPOSC_CTL 02118 " | C3FE0060 | RC_CTL 02119 " | C3FE0080 | LPRC_CTL 02120 " | C3FE00A0 | FMPLL_0 02121 " | C3FE00C0 | FMPLL_1 02122 " | - | Reserved 02123 MISC | C3FE0100 | CMU_0 & CMU_1 02124 02125 */ 02126 02127 /************************************/ 02128 /* OSC_CTL @ CGM base address + 0x0000 */ 02129 /************************************/ 02130 union { 02131 vuint32_t R; 02132 struct { 02133 vuint32_t OSCBYP:1; 02134 vuint32_t:7; 02135 vuint32_t EOCV:8; 02136 vuint32_t M_OSC:1; 02137 vuint32_t:2; 02138 vuint32_t OSCDIV:5; 02139 vuint32_t I_OSC:1; 02140 vuint32_t:5; 02141 vuint32_t S_OSC:1; 02142 vuint32_t OSCON:1; 02143 } B; 02144 } OSC_CTL; /* Main OSC Control Register */ 02145 02146 /************************************/ 02147 /* LPOSC_CTL @ CGM base address + 0x0040 */ 02148 /************************************/ 02149 int32_t CGM_reserved0[15]; /* (0x040 - 0x004)/4 = 0x0F */ 02150 /*int32_t $RESERVED[15]; */ 02151 02152 union { 02153 vuint32_t R; 02154 struct { 02155 vuint32_t OSCBYP:1; 02156 vuint32_t:7; 02157 vuint32_t EOCV:8; 02158 vuint32_t M_OSC:1; 02159 vuint32_t:2; 02160 vuint32_t OSCDIV:5; 02161 vuint32_t I_OSC:1; 02162 vuint32_t:5; 02163 vuint32_t S_OSC:1; 02164 vuint32_t OSCON:1; 02165 } B; 02166 } LPOSC_CTL; /* Low Power OSC Control Register */ 02167 02168 /************************************/ 02169 /* RC_CTL @ CGM base address + 0x0060 */ 02170 /************************************/ 02171 int32_t CGM_reserved1[7]; /* (0x060 - 0x044)/4 = 0x07 */ 02172 02173 union { 02174 vuint32_t R; 02175 struct { 02176 vuint32_t:10; 02177 vuint32_t RCTRIM:6; 02178 vuint32_t:3; 02179 vuint32_t RCDIV:5; 02180 vuint32_t:2; 02181 vuint32_t S_RC_STDBY:1; 02182 vuint32_t:5; 02183 } B; 02184 } RC_CTL; /* RC OSC Control Register */ 02185 02186 /*************************************/ 02187 /* LPRC_CTL @ CGM base address + 0x0080 */ 02188 /*************************************/ 02189 int32_t CGM_reserved2[7]; /* (0x080 - 0x064)/4 = 0x07 */ 02190 02191 union { 02192 vuint32_t R; 02193 struct { 02194 vuint32_t:11; 02195 vuint32_t LRCTRIM:5; 02196 vuint32_t:3; 02197 vuint32_t LPRCDIV:5; 02198 vuint32_t:3; 02199 vuint32_t S_LPRC:1; 02200 vuint32_t:3; 02201 vuint32_t LPRCON_STDBY:1; 02202 } B; 02203 } LPRC_CTL; /* Low Power RC OSC Control Register */ 02204 02205 /************************************/ 02206 /* FMPLL_0 @ CGM base address + 0x00A0 */ 02207 /* FMPLL_1 @ CGM base address + 0x0100 */ 02208 /************************************/ 02209 int32_t CGM_reserved3[7]; /* (0x0A0 - 0x084)/4 = 0x07 */ 02210 02211 struct { 02212 union { 02213 vuint32_t R; 02214 struct { 02215 vuint32_t:2; 02216 vuint32_t IDF:4; 02217 vuint32_t ODF:2; 02218 vuint32_t:1; 02219 vuint32_t NDIV:7; 02220 vuint32_t:7; 02221 vuint32_t EN_PLL_SW:1; 02222 vuint32_t MODE:1; 02223 vuint32_t UNLOCK_ONCE:1; 02224 vuint32_t:1; 02225 vuint32_t I_LOCK:1; 02226 vuint32_t S_LOCK:1; 02227 vuint32_t PLL_FAIL_MASK:1; 02228 vuint32_t PLL_FAIL_FLAG:1; 02229 vuint32_t:1; 02230 } B; 02231 } CR; /* FMPLL Control Register */ 02232 02233 union { 02234 vuint32_t R; 02235 struct { 02236 vuint32_t STRB_BYPASS:1; 02237 vuint32_t:1; 02238 vuint32_t SPRD_SEL:1; 02239 vuint32_t MOD_PERIOD:13; 02240 vuint32_t FM_EN:1; 02241 vuint32_t INC_STEP:15; 02242 } B; 02243 } MR; /* FMPLL Modulation Register */ 02244 02245 int32_t CGM_reserved4[6]; /* (0x0C0 - 0x0A8)/4 = 0x06 */ 02246 /* (0x0E0 - 0x0C8)/4 = 0x06 */ 02247 02248 } FMPLL[2]; 02249 02250 /************************************/ 02251 /* CMU @ CGM base address + 0x0100 */ 02252 /************************************/ 02253 int32_t CGM_reserved5[8]; /* (0x100 - 0x0E0)/4 = 0x08 */ 02254 02255 union { 02256 vuint32_t R; 02257 struct { 02258 vuint32_t:8; 02259 vuint32_t SFM:1; 02260 vuint32_t:13; 02261 vuint32_t CLKSEL1:2; 02262 vuint32_t:5; 02263 vuint32_t RCDIV:2; 02264 vuint32_t CME_A:1; 02265 } B; 02266 } CMU_0_CSR; /* Control Status Register */ 02267 02268 union { 02269 vuint32_t R; 02270 struct { 02271 vuint32_t:12; 02272 vuint32_t FD:20; 02273 } B; 02274 } CMU_0_FDR; /* Frequency Display Register */ 02275 02276 union { 02277 vuint32_t R; 02278 struct { 02279 vuint32_t:20; 02280 vuint32_t HFREF_A:12; 02281 } B; 02282 } CMU_0_HFREFR_A; /* High Frequency Reference Register PLL_A Register */ 02283 02284 union { 02285 vuint32_t R; 02286 struct { 02287 vuint32_t:20; 02288 vuint32_t LFREF_A:12; 02289 } B; 02290 } CMU_0_LFREFR_A; /* Low Frequency Reference Register PLL_A Register */ 02291 02292 union { 02293 vuint32_t R; 02294 struct { 02295 vuint32_t:28; 02296 vuint32_t FLCI_A:1; 02297 vuint32_t FHHI_A:1; 02298 vuint32_t FLLI_A:1; 02299 vuint32_t OLRI:1; 02300 } B; 02301 } CMU_0_ISR; /* Interrupt Status Register */ 02302 02303 union { 02304 vuint32_t R; 02305 struct { 02306 vuint32_t:32; 02307 } B; 02308 } CMU_0_IMR; /* Interrupt Mask Register */ 02309 02310 union { 02311 vuint32_t R; 02312 struct { 02313 vuint32_t:12; 02314 vuint32_t MD:20; 02315 } B; 02316 } CMU_0_MDR; /* Measurement Duration Register */ 02317 02318 int32_t CGM_reserved5A; /* (0x020 - 0x01C)/4 = 0x01 */ 02319 02320 union { 02321 vuint32_t R; 02322 struct { 02323 vuint32_t:8; 02324 vuint32_t SFM:1; 02325 vuint32_t:13; 02326 vuint32_t CLKSEL1:2; 02327 vuint32_t:5; 02328 vuint32_t RCDIV:2; 02329 vuint32_t CME_A:1; 02330 } B; 02331 } CMU_1_CSR; /* Control Status Register */ 02332 02333 int32_t CGM_reserved6; /* (0x028 - 0x024)/4 = 0x01 */ 02334 02335 union { 02336 vuint32_t R; 02337 struct { 02338 vuint32_t:20; 02339 vuint32_t HFREF_A:12; 02340 } B; 02341 } CMU_1_HFREFR_A; /* High Frequency Reference Register PLL_A Register */ 02342 02343 union { 02344 vuint32_t R; 02345 struct { 02346 vuint32_t:20; 02347 vuint32_t LFREF_A:12; 02348 } B; 02349 } CMU_1_LFREFR_A; /* Low Frequency Reference Register PLL_A Register */ 02350 02351 union { 02352 vuint32_t R; 02353 struct { 02354 vuint32_t:28; 02355 vuint32_t FLCI_A:1; 02356 vuint32_t FHHI_A:1; 02357 vuint32_t FLLI_A:1; 02358 vuint32_t:1; 02359 } B; 02360 } CMU_1_ISR; /* Interrupt Status Register */ 02361 02362 /************************************/ 02363 /* CGM General Registers @ CGM base address + 0x0370 */ 02364 /************************************/ 02365 int32_t CGM_reserved7[143]; /* (0x370 - 0x134)/4 = 0x8F */ 02366 02367 union { 02368 vuint32_t R; 02369 struct { 02370 vuint32_t:31; 02371 vuint32_t EN:1; 02372 } B; 02373 } OCEN; /* Output Clock Enable Register */ 02374 02375 union { 02376 vuint32_t R; 02377 struct { 02378 vuint32_t:2; 02379 vuint32_t SELDIV:2; 02380 vuint32_t SELCTL:4; 02381 vuint32_t:24; 02382 } B; 02383 } OCDSSC; /* Output Clock Division Select Register */ 02384 02385 union { 02386 vuint32_t R; 02387 struct { 02388 vuint32_t:4; 02389 vuint32_t SELSTAT:4; 02390 vuint32_t:24; 02391 } B; 02392 } SCSS; /* System Clock Select Status */ 02393 02394 union { 02395 vuint32_t R; 02396 struct { 02397 vuint32_t DE0:1; 02398 vuint32_t:3; 02399 vuint32_t DIV0:4; 02400 vuint32_t DE1:1; 02401 vuint32_t:3; 02402 vuint32_t DIV1:4; 02403 vuint32_t DE2:1; 02404 vuint32_t:3; 02405 vuint32_t DIV2:4; 02406 vuint32_t DE3:1; 02407 vuint32_t:3; 02408 vuint32_t DIV3:4; 02409 } B; 02410 } SCDC; /* GSystem Clock Divider Configuration 0->4 */ 02411 02412 union { 02413 vuint32_t R; 02414 struct { 02415 vuint32_t:4; 02416 vuint32_t SELCTL:4; 02417 vuint32_t:24; 02418 } B; 02419 } AC0SC; /* Aux Clock 0 Select Control */ 02420 02421 union { 02422 vuint32_t R; 02423 struct { 02424 vuint32_t DE0:1; 02425 vuint32_t:3; 02426 vuint32_t DIV0:4; 02427 vuint32_t DE1:1; 02428 vuint32_t:3; 02429 vuint32_t DIV1:4; 02430 vuint32_t DE2:1; 02431 vuint32_t:3; 02432 vuint32_t DIV2:4; 02433 vuint32_t DE3:1; 02434 vuint32_t:3; 02435 vuint32_t DIV3:4; 02436 } B; 02437 } AC0DC; /* Aux Clock 0 Divider Configuration 0->3 */ 02438 02439 union { 02440 vuint32_t R; 02441 struct { 02442 vuint32_t:4; 02443 vuint32_t SELCTL:4; 02444 vuint32_t:24; 02445 } B; 02446 } AC1SC; /* Aux Clock 1 Select Control */ 02447 02448 union { 02449 vuint32_t R; 02450 struct { 02451 vuint32_t DE0:1; 02452 vuint32_t:3; 02453 vuint32_t DIV0:4; 02454 vuint32_t DE1:1; 02455 vuint32_t:3; 02456 vuint32_t DIV1:4; 02457 vuint32_t DE2:1; 02458 vuint32_t:3; 02459 vuint32_t DIV2:4; 02460 vuint32_t DE3:1; 02461 vuint32_t:3; 02462 vuint32_t DIV3:4; 02463 } B; 02464 } AC1DC; /* Aux Clock 1 Divider Configuration 0->3 */ 02465 02466 union { 02467 vuint32_t R; 02468 struct { 02469 vuint32_t:4; 02470 vuint32_t SELCTL:4; 02471 vuint32_t:24; 02472 } B; 02473 } AC2SC; /* Aux Clock 2 Select Control */ 02474 02475 union { 02476 vuint32_t R; 02477 struct { 02478 vuint32_t DE0:1; 02479 vuint32_t:3; 02480 vuint32_t DIV0:4; 02481 vuint32_t DE1:1; 02482 vuint32_t:3; 02483 vuint32_t DIV1:4; 02484 vuint32_t DE2:1; 02485 vuint32_t:3; 02486 vuint32_t DIV2:4; 02487 vuint32_t DE3:1; 02488 vuint32_t:3; 02489 vuint32_t DIV3:4; 02490 } B; 02491 } AC2DC; /* Aux Clock 2 Divider Configuration 0->3 */ 02492 02493 union { 02494 vuint32_t R; 02495 struct { 02496 vuint32_t:4; 02497 vuint32_t SELCTL:4; 02498 vuint32_t:24; 02499 } B; 02500 } AC3SC; /* Aux Clock 3 Select Control */ 02501 02502 union { 02503 vuint32_t R; 02504 struct { 02505 vuint32_t DE0:1; 02506 vuint32_t:3; 02507 vuint32_t DIV0:4; 02508 vuint32_t DE1:1; 02509 vuint32_t:3; 02510 vuint32_t DIV1:4; 02511 vuint32_t DE2:1; 02512 vuint32_t:3; 02513 vuint32_t DIV2:4; 02514 vuint32_t DE3:1; 02515 vuint32_t:3; 02516 vuint32_t DIV3:4; 02517 } B; 02518 } AC3DC; /* Aux Clock 3 Divider Configuration 0->3 */ 02519 02520 union { 02521 vuint32_t R; 02522 struct { 02523 vuint32_t:4; 02524 vuint32_t SELCTL:4; 02525 vuint32_t:24; 02526 } B; 02527 } AC4SC; /* Aux Clock 4 Select Control */ 02528 02529 union { 02530 vuint32_t R; 02531 struct { 02532 vuint32_t DE0:1; 02533 vuint32_t:3; 02534 vuint32_t DIV0:4; 02535 vuint32_t DE1:1; 02536 vuint32_t:3; 02537 vuint32_t DIV1:4; 02538 vuint32_t DE2:1; 02539 vuint32_t:3; 02540 vuint32_t DIV2:4; 02541 vuint32_t DE3:1; 02542 vuint32_t:3; 02543 vuint32_t DIV3:4; 02544 } B; 02545 } AC4DC; /* Aux Clock 4 Divider Configuration 0->3 */ 02546 02547 union { 02548 vuint32_t R; 02549 struct { 02550 vuint32_t:4; 02551 vuint32_t SELCTL:4; 02552 vuint32_t:24; 02553 } B; 02554 } AC5SC; /* Aux Clock 5 Select Control */ 02555 02556 union { 02557 vuint32_t R; 02558 struct { 02559 vuint32_t DE0:1; 02560 vuint32_t:3; 02561 vuint32_t DIV0:4; 02562 vuint32_t DE1:1; 02563 vuint32_t:3; 02564 vuint32_t DIV1:4; 02565 vuint32_t DE2:1; 02566 vuint32_t:3; 02567 vuint32_t DIV2:4; 02568 vuint32_t DE3:1; 02569 vuint32_t:3; 02570 vuint32_t DIV3:4; 02571 } B; 02572 } AC5DC; /* Aux Clock 5 Divider Configuration 0->3 */ 02573 02574 union { 02575 vuint32_t R; 02576 struct { 02577 vuint32_t:4; 02578 vuint32_t SELCTL:4; 02579 vuint32_t:24; 02580 } B; 02581 } AC6SC; /* Aux Clock 6 Select Control */ 02582 02583 union { 02584 vuint32_t R; 02585 struct { 02586 vuint32_t DE0:1; 02587 vuint32_t:3; 02588 vuint32_t DIV0:4; 02589 vuint32_t DE1:1; 02590 vuint32_t:3; 02591 vuint32_t DIV1:4; 02592 vuint32_t DE2:1; 02593 vuint32_t:3; 02594 vuint32_t DIV2:4; 02595 vuint32_t DE3:1; 02596 vuint32_t:3; 02597 vuint32_t DIV3:4; 02598 } B; 02599 } AC6DC; /* Aux Clock 6 Divider Configuration 0->3 */ 02600 02601 union { 02602 vuint32_t R; 02603 struct { 02604 vuint32_t:4; 02605 vuint32_t SELCTL:4; 02606 vuint32_t:24; 02607 } B; 02608 } AC7SC; /* Aux Clock 7 Select Control */ 02609 02610 union { 02611 vuint32_t R; 02612 struct { 02613 vuint32_t DE0:1; 02614 vuint32_t:3; 02615 vuint32_t DIV0:4; 02616 vuint32_t DE1:1; 02617 vuint32_t:3; 02618 vuint32_t DIV1:4; 02619 vuint32_t DE2:1; 02620 vuint32_t:3; 02621 vuint32_t DIV2:4; 02622 vuint32_t DE3:1; 02623 vuint32_t:3; 02624 vuint32_t DIV3:4; 02625 } B; 02626 } AC7DC; /* Aux Clock 7 Divider Configuration 0->3 */ 02627 02628 union { 02629 vuint32_t R; 02630 struct { 02631 vuint32_t:4; 02632 vuint32_t SELCTL:4; 02633 vuint32_t:24; 02634 } B; 02635 } AC8SC; /* Aux Clock 8 Select Control */ 02636 02637 union { 02638 vuint32_t R; 02639 struct { 02640 vuint32_t DE0:1; 02641 vuint32_t:3; 02642 vuint32_t DIV0:4; 02643 vuint32_t DE1:1; 02644 vuint32_t:3; 02645 vuint32_t DIV1:4; 02646 vuint32_t DE2:1; 02647 vuint32_t:3; 02648 vuint32_t DIV2:4; 02649 vuint32_t DE3:1; 02650 vuint32_t:3; 02651 vuint32_t DIV3:4; 02652 } B; 02653 } AC8DC; /* Aux Clock 8 Divider Configuration 0->3 */ 02654 02655 union { 02656 vuint32_t R; 02657 struct { 02658 vuint32_t:4; 02659 vuint32_t SELCTL:4; 02660 vuint32_t:24; 02661 } B; 02662 } AC9SC; /* Aux Clock 9 Select Control */ 02663 02664 union { 02665 vuint32_t R; 02666 struct { 02667 vuint32_t DE0:1; 02668 vuint32_t:3; 02669 vuint32_t DIV0:4; 02670 vuint32_t DE1:1; 02671 vuint32_t:3; 02672 vuint32_t DIV1:4; 02673 vuint32_t DE2:1; 02674 vuint32_t:3; 02675 vuint32_t DIV2:4; 02676 vuint32_t DE3:1; 02677 vuint32_t:3; 02678 vuint32_t DIV3:4; 02679 } B; 02680 } AC9DC; /* Aux Clock 9 Divider Configuration 0->3 */ 02681 02682 union { 02683 vuint32_t R; 02684 struct { 02685 vuint32_t:4; 02686 vuint32_t SELCTL:4; 02687 vuint32_t:24; 02688 } B; 02689 } AC10SC; /* Aux Clock 10 Select Control */ 02690 02691 union { 02692 vuint32_t R; 02693 struct { 02694 vuint32_t DE0:1; 02695 vuint32_t:3; 02696 vuint32_t DIV0:4; 02697 vuint32_t DE1:1; 02698 vuint32_t:3; 02699 vuint32_t DIV1:4; 02700 vuint32_t DE2:1; 02701 vuint32_t:3; 02702 vuint32_t DIV2:4; 02703 vuint32_t DE3:1; 02704 vuint32_t:3; 02705 vuint32_t DIV3:4; 02706 } B; 02707 } AC10DC; /* Aux Clock 10 Divider Configuration 0->3 */ 02708 02709 union { 02710 vuint32_t R; 02711 struct { 02712 vuint32_t:4; 02713 vuint32_t SELCTL:4; 02714 vuint32_t:24; 02715 } B; 02716 } AC11SC; /* Aux Clock 11 Select Control */ 02717 02718 union { 02719 vuint32_t R; 02720 struct { 02721 vuint32_t DE0:1; 02722 vuint32_t:3; 02723 vuint32_t DIV0:4; 02724 vuint32_t DE1:1; 02725 vuint32_t:3; 02726 vuint32_t DIV1:4; 02727 vuint32_t DE2:1; 02728 vuint32_t:3; 02729 vuint32_t DIV2:4; 02730 vuint32_t DE3:1; 02731 vuint32_t:3; 02732 vuint32_t DIV3:4; 02733 } B; 02734 } AC11DC; /* Aux Clock 11 Divider Configuration 0->3 */ 02735 02736 union { 02737 vuint32_t R; 02738 struct { 02739 vuint32_t:4; 02740 vuint32_t SELCTL:4; 02741 vuint32_t:24; 02742 } B; 02743 } AC12SC; /* Aux Clock 12 Select Control */ 02744 02745 union { 02746 vuint32_t R; 02747 struct { 02748 vuint32_t DE0:1; 02749 vuint32_t:3; 02750 vuint32_t DIV0:4; 02751 vuint32_t DE1:1; 02752 vuint32_t:3; 02753 vuint32_t DIV1:4; 02754 vuint32_t DE2:1; 02755 vuint32_t:3; 02756 vuint32_t DIV2:4; 02757 vuint32_t DE3:1; 02758 vuint32_t:3; 02759 vuint32_t DIV3:4; 02760 } B; 02761 } AC12DC; /* Aux Clock 12 Divider Configuration 0->3 */ 02762 02763 union { 02764 vuint32_t R; 02765 struct { 02766 vuint32_t:4; 02767 vuint32_t SELCTL:4; 02768 vuint32_t:24; 02769 } B; 02770 } AC13SC; /* Aux Clock 13 Select Control */ 02771 02772 union { 02773 vuint32_t R; 02774 struct { 02775 vuint32_t DE0:1; 02776 vuint32_t:3; 02777 vuint32_t DIV0:4; 02778 vuint32_t DE1:1; 02779 vuint32_t:3; 02780 vuint32_t DIV1:4; 02781 vuint32_t DE2:1; 02782 vuint32_t:3; 02783 vuint32_t DIV2:4; 02784 vuint32_t DE3:1; 02785 vuint32_t:3; 02786 vuint32_t DIV3:4; 02787 } B; 02788 } AC13DC; /* Aux Clock 13 Divider Configuration 0->3 */ 02789 02790 union { 02791 vuint32_t R; 02792 struct { 02793 vuint32_t:4; 02794 vuint32_t SELCTL:4; 02795 vuint32_t:24; 02796 } B; 02797 } AC14SC; /* Aux Clock 14 Select Control */ 02798 02799 union { 02800 vuint32_t R; 02801 struct { 02802 vuint32_t DE0:1; 02803 vuint32_t:3; 02804 vuint32_t DIV0:4; 02805 vuint32_t DE1:1; 02806 vuint32_t:3; 02807 vuint32_t DIV1:4; 02808 vuint32_t DE2:1; 02809 vuint32_t:3; 02810 vuint32_t DIV2:4; 02811 vuint32_t DE3:1; 02812 vuint32_t:3; 02813 vuint32_t DIV3:4; 02814 } B; 02815 } AC14DC; /* Aux Clock 14 Divider Configuration 0->3 */ 02816 02817 union { 02818 vuint32_t R; 02819 struct { 02820 vuint32_t:4; 02821 vuint32_t SELCTL:4; 02822 vuint32_t:24; 02823 } B; 02824 } AC15SC; /* Aux Clock 15 Select Control */ 02825 02826 union { 02827 vuint32_t R; 02828 struct { 02829 vuint32_t DE0:1; 02830 vuint32_t:3; 02831 vuint32_t DIV0:4; 02832 vuint32_t DE1:1; 02833 vuint32_t:3; 02834 vuint32_t DIV1:4; 02835 vuint32_t DE2:1; 02836 vuint32_t:3; 02837 vuint32_t DIV2:4; 02838 vuint32_t DE3:1; 02839 vuint32_t:3; 02840 vuint32_t DIV3:4; 02841 } B; 02842 } AC15DC; /* Aux Clock 15 Divider Configuration 0->3 */ 02843 02844 }; /* end of CGM_tag */ 02845 /****************************************************************************/ 02846 /* MODULE : RGM */ 02847 /****************************************************************************/ 02848 struct RGM_tag { 02849 02850 union { 02851 vuint16_t R; 02852 struct { 02853 vuint16_t F_EXR:1; 02854 vuint16_t:3; 02855 vuint16_t F_CMU1_FHL:1; 02856 vuint16_t:1; 02857 vuint16_t F_PLL1:1; 02858 vuint16_t F_FLASH:1; 02859 vuint16_t F_LVD45:1; 02860 vuint16_t F_CMU0_FHL:1; 02861 vuint16_t F_CMU0_OLR:1; 02862 vuint16_t F_PLL0:1; 02863 vuint16_t F_CHKSTOP:1; 02864 vuint16_t F_SOFT:1; 02865 vuint16_t F_CORE:1; 02866 vuint16_t F_JTAG:1; 02867 } B; 02868 } FES; /* Functional Event Status */ 02869 02870 union { 02871 vuint16_t R; 02872 struct { 02873 vuint16_t POR:1; 02874 vuint16_t:7; 02875 vuint16_t F_COMP:1; 02876 vuint16_t F_LVD27_IO:1; 02877 vuint16_t F_LVD27_FLASH:1; 02878 vuint16_t F_LVD27_VREG:1; 02879 vuint16_t F_LVD27:1; 02880 vuint16_t F_SWT:1; 02881 vuint16_t F_LVD12_PD1:1; 02882 vuint16_t F_LVD12_PD0:1; 02883 } B; 02884 } DES; /* Destructive Event Status */ 02885 02886 union { 02887 vuint16_t R; 02888 struct { 02889 vuint16_t D_EXR:1; 02890 vuint16_t:3; 02891 vuint16_t D_CMU1_FHL:1; 02892 vuint16_t:1; 02893 vuint16_t D_PLL1:1; 02894 vuint16_t D_FLASH:1; 02895 vuint16_t D_LVD45:1; 02896 vuint16_t D_CMU0_FHL:1; 02897 vuint16_t D_CMU0_OLR:1; 02898 vuint16_t D_PLL0:1; 02899 vuint16_t D_CHKSTOP:1; 02900 vuint16_t D_SOFT:1; 02901 vuint16_t D_CORE:1; 02902 vuint16_t D_JTAG:1; 02903 } B; 02904 } FERD; /* Functional Event Reset Disable */ 02905 02906 union { 02907 vuint16_t R; 02908 struct { 02909 vuint16_t:8; 02910 vuint16_t D_COMP:1; 02911 vuint16_t D_LVD27_IO:1; 02912 vuint16_t D_LVD27_FLASH:1; 02913 vuint16_t D_LVD27_VREG:1; 02914 vuint16_t D_LVD27:1; 02915 vuint16_t D_SWT:1; 02916 vuint16_t D_LVD12_PD1:1; 02917 vuint16_t D_LVD12_PD0:1; 02918 } B; 02919 } DERD; /* Destructive Event Reset Disable */ 02920 02921 int16_t RGM_reserved0[4]; 02922 02923 union { 02924 vuint16_t R; 02925 struct { 02926 vuint16_t:4; 02927 vuint16_t AR_CMU1_FHL:1; 02928 vuint16_t:1; 02929 vuint16_t AR_PLL1:1; 02930 vuint16_t AR_FLASH:1; 02931 vuint16_t AR_LVD45:1; 02932 vuint16_t AR_CMU0_FHL:1; 02933 vuint16_t AR_CMU0_OLR:1; 02934 vuint16_t AR_PLL0:1; 02935 vuint16_t AR_CHKSTOP:1; 02936 vuint16_t AR_SOFT:1; 02937 vuint16_t AR_CORE:1; 02938 vuint16_t AR_JTAG:1; 02939 } B; 02940 } FEAR; /* Functional Event Alternate Request */ 02941 02942 union { 02943 vuint16_t R; 02944 struct { 02945 vuint16_t:8; 02946 vuint16_t AR_COMP:1; 02947 vuint16_t AR_LVD27_IO:1; 02948 vuint16_t AR_LVD27_FLASH:1; 02949 vuint16_t AR_LVD27_VREG:1; 02950 vuint16_t AR_LVD27:1; 02951 vuint16_t AR_SWT:1; 02952 vuint16_t AR_LVD12_PD1:1; 02953 vuint16_t AR_LVD12_PD0:1; 02954 } B; 02955 } DEAR; /* Destructive Event Alternate Request */ 02956 02957 int16_t RGM_reserved1[2]; 02958 02959 union { 02960 vuint16_t R; 02961 struct { 02962 vuint16_t:4; 02963 vuint16_t SS_CMU1_FHL:1; 02964 vuint16_t:1; 02965 vuint16_t SS_PLL1:1; 02966 vuint16_t SS_FLASH:1; 02967 vuint16_t SS_LVD45:1; 02968 vuint16_t SS_CMU0_FHL:1; 02969 vuint16_t SS_CMU0_OLR:1; 02970 vuint16_t SS_PLL0:1; 02971 vuint16_t SS_CHKSTOP:1; 02972 vuint16_t SS_SOFT:1; 02973 vuint16_t SS_CORE:1; 02974 vuint16_t SS_JTAG:1; 02975 } B; 02976 } FESS; /* Functional Event Short Sequence */ 02977 02978 union { 02979 vuint16_t R; 02980 struct { 02981 vuint16_t:8; 02982 vuint16_t BOOT:1; 02983 vuint16_t:4; 02984 vuint16_t DRUND_FLA:1; 02985 vuint16_t:1; 02986 vuint16_t DRUNC_FLA:1; 02987 } B; 02988 } STDBY; /* STANDBY reset sequence */ 02989 02990 union { 02991 vuint16_t R; 02992 struct { 02993 vuint16_t:4; 02994 vuint16_t BE_CMU1_FHL:1; 02995 vuint16_t:1; 02996 vuint16_t BE_PLL1:1; 02997 vuint16_t BE_FLASH:1; 02998 vuint16_t BE_LVD45:1; 02999 vuint16_t BE_CMU0_FHL:1; 03000 vuint16_t BE_CMU0_OLR:1; 03001 vuint16_t BE_PLL0:1; 03002 vuint16_t BE_CHKSTOP:1; 03003 vuint16_t BE_SOFT:1; 03004 vuint16_t BE_CORE:1; 03005 vuint16_t BE_JTAG:1; 03006 } B; 03007 } FBRE; /* Functional Bidirectional Reset Enable */ 03008 03009 }; /* end of RGM_tag */ 03010 /****************************************************************************/ 03011 /* MODULE : PCU */ 03012 /****************************************************************************/ 03013 struct PCU_tag { 03014 03015 union { 03016 vuint32_t R; 03017 struct { 03018 vuint32_t:18; 03019 vuint32_t STBY0:1; 03020 vuint32_t:2; 03021 vuint32_t STOP0:1; 03022 vuint32_t:1; 03023 vuint32_t HALT0:1; 03024 vuint32_t RUN3:1; 03025 vuint32_t RUN2:1; 03026 vuint32_t RUN1:1; 03027 vuint32_t RUN0:1; 03028 vuint32_t DRUN:1; 03029 vuint32_t SAFE:1; 03030 vuint32_t TEST:1; 03031 vuint32_t RST:1; 03032 } B; 03033 } PCONF[16]; /* Power domain 0-15 configuration register */ 03034 03035 union { 03036 vuint32_t R; 03037 struct { 03038 vuint32_t:16; 03039 vuint32_t PD15:1; 03040 vuint32_t PD14:1; 03041 vuint32_t PD13:1; 03042 vuint32_t PD12:1; 03043 vuint32_t PD11:1; 03044 vuint32_t PD10:1; 03045 vuint32_t PD9:1; 03046 vuint32_t PD8:1; 03047 vuint32_t PD7:1; 03048 vuint32_t PD6:1; 03049 vuint32_t PD5:1; 03050 vuint32_t PD4:1; 03051 vuint32_t PD3:1; 03052 vuint32_t PD2:1; 03053 vuint32_t PD1:1; 03054 vuint32_t PD0:1; 03055 } B; 03056 } PSTAT; /* Power Domain Status Register */ 03057 03058 int32_t PCU_reserved0[15]; /* {0x0080-0x0044}/0x4 = 0xF */ 03059 03060 union { 03061 vuint32_t R; 03062 struct { 03063 vuint32_t:15; 03064 vuint32_t MASK_LVDHV5:1; 03065 } B; 03066 } VCTL; /* Voltage Regulator Control Register */ 03067 03068 }; /* end of PCU_tag */ 03069 /****************************************************************************/ 03070 /* MODULE : FLEXPWM */ 03071 /****************************************************************************/ 03072 struct FLEXPWM_SUB_tag { 03073 03074 union { 03075 vuint16_t R; 03076 } CNT; /* Counter Register */ 03077 03078 union { 03079 vuint16_t R; 03080 } INIT; /* Initial Count Register */ 03081 03082 union { 03083 vuint16_t R; 03084 struct { 03085 vuint16_t DBGEN:1; 03086 vuint16_t WAITEN:1; 03087 vuint16_t INDEP:1; 03088 vuint16_t PWMA_INIT:1; 03089 vuint16_t PWMB_INIT:1; 03090 vuint16_t PWMX_INIT:1; 03091 vuint16_t INIT_SEL:2; 03092 vuint16_t FRCEN:1; 03093 vuint16_t FORCE:1; 03094 vuint16_t FORCE_SEL:3; 03095 vuint16_t RELOAD_SEL:1; 03096 vuint16_t CLK_SEL:2; 03097 } B; 03098 } CTRL2; /* Control 2 Register */ 03099 03100 union { 03101 vuint16_t R; 03102 struct { 03103 vuint16_t LDFQ:4; 03104 vuint16_t HALF:1; 03105 vuint16_t FULL:1; 03106 vuint16_t DT:2; 03107 vuint16_t:1; 03108 vuint16_t PRSC:3; 03109 vuint16_t:3; 03110 vuint16_t DBLEN:1; 03111 } B; 03112 } CTRL; /* Control Register */ 03113 03114 union { 03115 vuint16_t R; 03116 } VAL[6]; /* Value Register 0->5 */ 03117 03118 union { 03119 vuint16_t R; 03120 struct { 03121 vuint16_t FRACAEN:1; 03122 vuint16_t:10; 03123 vuint16_t FRACADLY:5; 03124 } B; 03125 } FRACA; /* Fractional Delay Register A */ 03126 03127 union { 03128 vuint16_t R; 03129 struct { 03130 vuint16_t FRACBEN:1; 03131 vuint16_t:10; 03132 vuint16_t FRACBDLY:5; 03133 } B; 03134 } FRACB; /* Fractional Delay Register B */ 03135 03136 union { 03137 vuint16_t R; 03138 struct { 03139 vuint16_t PWMA_IN:1; 03140 vuint16_t PWMB_IN:1; 03141 vuint16_t PWMX_IN:1; 03142 vuint16_t:2; 03143 vuint16_t POLA:1; 03144 vuint16_t POLB:1; 03145 vuint16_t POLX:1; 03146 vuint16_t:2; 03147 vuint16_t PWMAFS:2; 03148 vuint16_t PWMBFS:2; 03149 vuint16_t PWMXFS:2; 03150 } B; 03151 } OCTRL; /* Output Control Register */ 03152 03153 union { 03154 vuint16_t R; 03155 struct { 03156 vuint16_t:1; 03157 vuint16_t RUF:1; 03158 vuint16_t REF:1; 03159 vuint16_t RF:1; 03160 vuint16_t CFA1:1; 03161 vuint16_t CFA0:1; 03162 vuint16_t CFB1:1; 03163 vuint16_t CFB0:1; 03164 vuint16_t CFX1:1; 03165 vuint16_t CFX0:1; 03166 vuint16_t CMPF:6; 03167 } B; 03168 } STS; /* Status Register */ 03169 03170 union { 03171 vuint16_t R; 03172 struct { 03173 vuint16_t:2; 03174 vuint16_t REIE:1; 03175 vuint16_t RIE:1; 03176 vuint16_t:4; 03177 vuint16_t CX1IE:1; 03178 vuint16_t CX0IE:1; 03179 vuint16_t CMPIE:6; 03180 } B; 03181 } INTEN; /* Interrupt Enable Register */ 03182 03183 union { 03184 vuint16_t R; 03185 struct { 03186 vuint16_t:6; 03187 vuint16_t VALDE:1; 03188 vuint16_t FAND:1; 03189 vuint16_t CAPTDE:2; 03190 vuint16_t CA1DE:1; 03191 vuint16_t CA0DE:1; 03192 vuint16_t CB1DE:1; 03193 vuint16_t CB0DE:1; 03194 vuint16_t CX1DE:1; 03195 vuint16_t CX0DE:1; 03196 } B; 03197 } DMAEN; /* DMA Enable Register */ 03198 03199 union { 03200 vuint16_t R; 03201 struct { 03202 vuint16_t:10; 03203 vuint16_t OUT_TRIG_EN:6; 03204 } B; 03205 } TCTRL; /* Output Trigger Control Register */ 03206 03207 union { 03208 vuint16_t R; 03209 struct { 03210 vuint16_t:4; 03211 vuint16_t DISX:4; 03212 vuint16_t DISB:4; 03213 vuint16_t DISA:4; 03214 } B; 03215 } DISMAP; /* Fault Disable Mapping Register */ 03216 03217 union { 03218 vuint16_t R; 03219 struct { 03220 vuint16_t:5; 03221 vuint16_t DTCNT0:11; 03222 } B; 03223 } DTCNT0; /* Deadtime Count Register 0 */ 03224 03225 union { 03226 vuint16_t R; 03227 struct { 03228 vuint16_t:5; 03229 vuint16_t DTCNT1:11; 03230 } B; 03231 } DTCNT1; /* Deadtime Count Register 1 */ 03232 03233 union { 03234 vuint16_t R; 03235 struct { 03236 vuint16_t CA1CNT:3; 03237 vuint16_t CA0CNT:3; 03238 vuint16_t CFAWM:2; 03239 vuint16_t EDGCNTAEN:1; 03240 vuint16_t INPSELA:1; 03241 vuint16_t EDGA1:2; 03242 vuint16_t EDGA0:2; 03243 vuint16_t ONESHOTA:1; 03244 vuint16_t ARMA:1; 03245 } B; 03246 } CAPTCTRLA; /* Capture Control Register A */ 03247 03248 union { 03249 vuint16_t R; 03250 struct { 03251 vuint16_t EDGCNTA:8; 03252 vuint16_t EDGCMPA:8; 03253 } B; 03254 } CAPTCOMPA; /* Capture Compare Register A */ 03255 03256 union { 03257 vuint16_t R; 03258 struct { 03259 vuint16_t CB1CNT:3; 03260 vuint16_t CB0CNT:3; 03261 vuint16_t CFBWM:2; 03262 vuint16_t EDGCNTBEN:1; 03263 vuint16_t INPSELB:1; 03264 vuint16_t EDGB1:2; 03265 vuint16_t EDGB0:2; 03266 vuint16_t ONESHOTB:1; 03267 vuint16_t ARMB:1; 03268 } B; 03269 } CAPTCTRLB; /* Capture Control Register B */ 03270 03271 union { 03272 vuint16_t R; 03273 struct { 03274 vuint16_t EDGCNTB:8; 03275 vuint16_t EDGCMPB:8; 03276 } B; 03277 } CAPTCOMPB; /* Capture Compare Register B */ 03278 03279 union { 03280 vuint16_t R; 03281 struct { 03282 vuint16_t CX1CNT:3; 03283 vuint16_t CX0CNT:3; 03284 vuint16_t CFXWM:2; 03285 vuint16_t EDGCNTX_EN:1; 03286 vuint16_t INP_SELX:1; 03287 vuint16_t EDGX1:2; 03288 vuint16_t EDGX0:2; 03289 vuint16_t ONESHOTX:1; 03290 vuint16_t ARMX:1; 03291 } B; 03292 } CAPTCTRLX; /* Capture Control Register B */ 03293 03294 union { 03295 vuint16_t R; 03296 struct { 03297 vuint16_t EDGCNTX:8; 03298 vuint16_t EDGCMPX:8; 03299 } B; 03300 } CAPTCOMPX; /* Capture Compare Register X */ 03301 03302 union { 03303 vuint16_t R; 03304 struct { 03305 vuint16_t CAPTVAL0:16; 03306 } B; 03307 } CVAL0; /* Capture Value 0 Register */ 03308 03309 union { 03310 vuint16_t R; 03311 struct { 03312 vuint16_t:12; 03313 vuint16_t CVAL0CYC:4; 03314 } B; 03315 } CVAL0C; /* Capture Value 0 Cycle Register */ 03316 03317 union { 03318 vuint16_t R; 03319 struct { 03320 vuint16_t CAPTVAL1:16; 03321 } B; 03322 } CVAL1; /* Capture Value 1 Register */ 03323 03324 union { 03325 vuint16_t R; 03326 struct { 03327 vuint16_t:12; 03328 vuint16_t CVAL1CYC:4; 03329 } B; 03330 } CVAL1C; /* Capture Value 1 Cycle Register */ 03331 03332 union { 03333 vuint16_t R; 03334 struct { 03335 vuint16_t CAPTVAL2:16; 03336 } B; 03337 } CVAL2; /* Capture Value 2 Register */ 03338 03339 union { 03340 vuint16_t R; 03341 struct { 03342 vuint16_t:12; 03343 vuint16_t CVAL2CYC:4; 03344 } B; 03345 } CVAL2C; /* Capture Value 2 Cycle Register */ 03346 03347 union { 03348 vuint16_t R; 03349 struct { 03350 vuint16_t CAPTVAL3:16; 03351 } B; 03352 } CVAL3; /* Capture Value 3 Register */ 03353 03354 union { 03355 vuint16_t R; 03356 struct { 03357 vuint16_t:12; 03358 vuint16_t CVAL3CYC:4; 03359 } B; 03360 } CVAL3C; /* Capture Value 3 Cycle Register */ 03361 03362 union { 03363 vuint16_t R; 03364 struct { 03365 vuint16_t CAPTVAL4:16; 03366 } B; 03367 } CVAL4; /* Capture Value 4 Register */ 03368 03369 union { 03370 vuint16_t R; 03371 struct { 03372 vuint16_t:12; 03373 vuint16_t CVAL4CYC:4; 03374 } B; 03375 } CVAL4C; /* Capture Value 4 Cycle Register */ 03376 03377 union { 03378 vuint16_t R; 03379 struct { 03380 vuint16_t CAPTVAL5:16; 03381 } B; 03382 } CVAL5; /* Capture Value 5 Register */ 03383 03384 union { 03385 vuint16_t R; 03386 struct { 03387 vuint16_t:12; 03388 vuint16_t CVAL5CYC:4; 03389 } B; 03390 } CVAL5C; /* Capture Value 5 Cycle Register */ 03391 03392 uint32_t FLEXPWM_SUB_reserved0; /* (0x04A - 0x050)/4 = 0x01 */ 03393 03394 }; /* end of FLEXPWM_SUB_tag */ 03395 03396 struct FLEXPWM_tag { 03397 03398 /* eg. FLEXPWM.SUB<[x]>.CNT.R {x = 0->3} */ 03399 struct FLEXPWM_SUB_tag SUB[4]; 03400 03401 union { 03402 vuint16_t R; 03403 struct { 03404 vuint16_t:4; 03405 vuint16_t PWMA_EN:4; 03406 vuint16_t PWMB_EN:4; 03407 vuint16_t PWMX_EN:4; 03408 } B; 03409 } OUTEN; /* Output Enable Register */ 03410 03411 union { 03412 vuint16_t R; 03413 struct { 03414 vuint16_t:4; 03415 vuint16_t MASKA:4; 03416 vuint16_t MASKB:4; 03417 vuint16_t MASKX:4; 03418 } B; 03419 } MASK; /* Output Mask Register */ 03420 03421 union { 03422 vuint16_t R; 03423 struct { 03424 vuint16_t:8; 03425 vuint16_t OUTA_3:1; 03426 vuint16_t OUTB_3:1; 03427 vuint16_t OUTA_2:1; 03428 vuint16_t OUTB_2:1; 03429 vuint16_t OUTA_1:1; 03430 vuint16_t OUTB_1:1; 03431 vuint16_t OUTA_0:1; 03432 vuint16_t OUTB_0:1; 03433 } B; 03434 } SWCOUT; /* Software Controlled Output Register */ 03435 03436 union { 03437 vuint16_t R; 03438 struct { 03439 vuint16_t SELA_3:2; 03440 vuint16_t SELB_3:2; 03441 vuint16_t SELA_2:2; 03442 vuint16_t SELB_2:2; 03443 vuint16_t SELA_1:2; 03444 vuint16_t SELB_1:2; 03445 vuint16_t SELA_0:2; 03446 vuint16_t SELB_0:2; 03447 } B; 03448 } DTSRCSEL; /* Deadtime Source Select Register */ 03449 03450 union { 03451 vuint16_t R; 03452 struct { 03453 vuint16_t IPOL:4; 03454 vuint16_t RUN:4; 03455 vuint16_t CLDOK:4; 03456 vuint16_t LDOK:4; 03457 } B; 03458 } MCTRL; /* Master Control Register */ 03459 03460 int16_t FLEXPWM_reserved1; 03461 03462 union { 03463 vuint16_t R; 03464 struct { 03465 vuint16_t FLVL:4; 03466 vuint16_t FAUTO:4; 03467 vuint16_t FSAFE:4; 03468 vuint16_t FIE:4; 03469 } B; 03470 } FCTRL; /* Fault Control Register */ 03471 03472 union { 03473 vuint16_t R; 03474 struct { 03475 vuint16_t:3; 03476 vuint16_t FTEST:1; 03477 vuint16_t FFPIN:4; 03478 vuint16_t:4; 03479 vuint16_t FFLAG:4; 03480 } B; 03481 } FSTS; /* Fault Status Register */ 03482 03483 union { 03484 vuint16_t R; 03485 struct { 03486 vuint16_t:5; 03487 vuint16_t FILT_CNT:3; 03488 vuint16_t FILT_PER:8; 03489 } B; 03490 } FFILT; /* Fault FilterRegister */ 03491 03492 }; /* end of FLEXPWM_tag */ 03493 /****************************************************************************/ 03494 /* MODULE : ETIMER */ 03495 /****************************************************************************/ 03496 struct ETIMER_CHANNEL_tag { 03497 03498 union { 03499 vuint16_t R; 03500 struct { 03501 vuint16_t COMP1:16; 03502 } B; 03503 } COMP1; /* Compare Register 1 */ 03504 03505 union { 03506 vuint16_t R; 03507 struct { 03508 vuint16_t COMP2:16; 03509 } B; 03510 } COMP2; /* Compare Register 2 */ 03511 03512 union { 03513 vuint16_t R; 03514 struct { 03515 vuint16_t CAPT1:16; 03516 } B; 03517 } CAPT1; /* Capture Register 1 */ 03518 03519 union { 03520 vuint16_t R; 03521 struct { 03522 vuint16_t CAPT2:16; 03523 } B; 03524 } CAPT2; /* Capture Register 2 */ 03525 03526 union { 03527 vuint16_t R; 03528 struct { 03529 vuint16_t LOAD:16; 03530 } B; 03531 } LOAD; /* Load Register */ 03532 03533 union { 03534 vuint16_t R; 03535 struct { 03536 vuint16_t HOLD:16; 03537 } B; 03538 } HOLD; /* Hold Register */ 03539 03540 union { 03541 vuint16_t R; 03542 struct { 03543 vuint16_t CNTR:16; 03544 } B; 03545 } CNTR; /* Counter Register */ 03546 03547 union { 03548 vuint16_t R; 03549 struct { 03550 vuint16_t CNTMODE:3; 03551 vuint16_t PRISRC:5; 03552 vuint16_t ONCE:1; 03553 vuint16_t LENGTH:1; 03554 vuint16_t DIR:1; 03555 vuint16_t SECSRC:5; 03556 } B; 03557 } CTRL; /* Control Register */ 03558 03559 union { 03560 vuint16_t R; 03561 struct { 03562 vuint16_t OEN:1; 03563 vuint16_t RDNT:1; 03564 vuint16_t INPUT:1; 03565 vuint16_t VAL:1; 03566 vuint16_t FORCE:1; 03567 vuint16_t COFRC:1; 03568 vuint16_t COINIT:2; 03569 vuint16_t SIPS:1; 03570 vuint16_t PIPS:1; 03571 vuint16_t OPS:1; 03572 vuint16_t MSTR:1; 03573 vuint16_t OUTMODE:4; 03574 } B; 03575 } CTRL2; /* Control Register 2 */ 03576 03577 union { 03578 vuint16_t R; 03579 struct { 03580 vuint16_t STPEN:1; 03581 vuint16_t ROC:2; 03582 vuint16_t FMODE:1; 03583 vuint16_t FDIS:4; 03584 vuint16_t C2FCNT:3; 03585 vuint16_t C1FCNT:3; 03586 vuint16_t DBGEN:2; 03587 } B; 03588 } CTRL3; /* Control Register 3 */ 03589 03590 union { 03591 vuint16_t R; 03592 struct { 03593 vuint16_t:6; 03594 vuint16_t WDF:1; 03595 vuint16_t RCF:1; 03596 vuint16_t ICF2:1; 03597 vuint16_t ICF1:1; 03598 vuint16_t IEHF:1; 03599 vuint16_t IELF:1; 03600 vuint16_t TOF:1; 03601 vuint16_t TCF2:1; 03602 vuint16_t TCF1:1; 03603 vuint16_t TCF:1; 03604 } B; 03605 } STS; /* Status Register */ 03606 03607 union { 03608 vuint16_t R; 03609 struct { 03610 vuint16_t ICF2DE:1; 03611 vuint16_t ICF1DE:1; 03612 vuint16_t CMPLD2DE:1; 03613 vuint16_t CMPLD1DE:1; 03614 vuint16_t:2; 03615 vuint16_t WDFIE:1; 03616 vuint16_t RCFIE:1; 03617 vuint16_t ICF2IE:1; 03618 vuint16_t ICF1IE:1; 03619 vuint16_t IEHFIE:1; 03620 vuint16_t IELFIE:1; 03621 vuint16_t TOFIE:1; 03622 vuint16_t TCF2IE:1; 03623 vuint16_t TCF1IE:1; 03624 vuint16_t TCFIE:1; 03625 } B; 03626 } INTDMA; /* Interrupt and DMA Register */ 03627 03628 union { 03629 vuint16_t R; 03630 struct { 03631 vuint16_t CMPLD1:16; 03632 } B; 03633 } CMPLD1; /* Compare Load Register 1 */ 03634 03635 union { 03636 vuint16_t R; 03637 struct { 03638 vuint16_t CMPLD2:16; 03639 } B; 03640 } CMPLD2; /* Compare Load Register 2 */ 03641 03642 union { 03643 vuint16_t R; 03644 struct { 03645 vuint16_t CLC2:3; 03646 vuint16_t CLC1:3; 03647 vuint16_t CMPMODE:2; 03648 vuint16_t CPT2MODE:2; 03649 vuint16_t CPT1MODE:2; 03650 vuint16_t CFWM:2; 03651 vuint16_t ONESHOT:1; 03652 vuint16_t ARM:1; 03653 } B; 03654 } CCCTRL; /* Compare and Capture Control Register */ 03655 03656 union { 03657 vuint16_t R; 03658 struct { 03659 vuint16_t:5; 03660 vuint16_t FILTCNT:3; 03661 vuint16_t FILTPER:8; 03662 } B; 03663 } FILT; /* Input Filter Register */ 03664 03665 }; /* end of ETIMER_CHANNEL_tag */ 03666 03667 struct ETIMER_tag { 03668 03669 struct ETIMER_CHANNEL_tag CHANNEL[8]; 03670 03671 union { 03672 vuint16_t R; 03673 struct { 03674 vuint16_t WDTOL:16; 03675 } B; 03676 } WDTOL; /* Watchdog Time-out Low Register */ 03677 03678 union { 03679 vuint16_t R; 03680 struct { 03681 vuint16_t WDTOH:16; 03682 } B; 03683 } WDTOH; /* Watchdog Time-out High Register */ 03684 03685 union { 03686 vuint16_t R; 03687 struct { 03688 vuint16_t:3; 03689 vuint16_t FTEST:1; 03690 vuint16_t FIE:4; 03691 vuint16_t:4; 03692 vuint16_t FLVL:4; 03693 } B; 03694 } FCTRL; /* Fault Control Register */ 03695 03696 union { 03697 vuint16_t R; 03698 struct { 03699 vuint16_t:4; 03700 vuint16_t FFPIN:4; 03701 vuint16_t:4; 03702 vuint16_t FFLAG:4; 03703 } B; 03704 } FSTS; /* Fault Status Register */ 03705 03706 union { 03707 vuint16_t R; 03708 struct { 03709 vuint16_t:5; 03710 vuint16_t FFILTCNT:3; 03711 vuint16_t FFILTPER:8; 03712 } B; 03713 } FFILT; /* Fault Filter Register */ 03714 03715 int16_t ETIMER_reserved1; 03716 03717 union { 03718 vuint16_t R; 03719 struct { 03720 vuint16_t:8; 03721 vuint16_t ENBL:8; 03722 } B; 03723 } ENBL; /* Channel Enable Register */ 03724 03725 int16_t ETIMER_reserved2; 03726 03727 union { 03728 vuint16_t R; 03729 struct { 03730 vuint16_t:11; 03731 vuint16_t DREQ:5; 03732 } B; 03733 } DREQ[4]; /* DMA Request 0->3 Select Register */ 03734 03735 }; /* end of ETIMER_tag */ 03736 /****************************************************************************/ 03737 /* MODULE : DCU */ 03738 /****************************************************************************/ 03739 struct DCU_LAYER_tag { 03740 03741 union { 03742 vuint32_t R; 03743 struct { 03744 vuint32_t:6; 03745 vuint32_t HEIGHT:10; 03746 vuint32_t:8; 03747 vuint32_t WIDTH:8; 03748 } B; 03749 } CTRLDESCL1; /* LAYER[X].CTRLDESCL1 */ 03750 03751 union { 03752 vuint32_t R; 03753 struct { 03754 vuint32_t:6; 03755 vuint32_t POSY:10; 03756 vuint32_t:8; 03757 vuint32_t POSX:8; 03758 } B; 03759 } CTRLDESCL2; /* LAYER[X].CTRLDESCL2 */ 03760 03761 union { 03762 vuint32_t R; 03763 struct { 03764 vuint32_t ADDR:32; 03765 } B; 03766 } CTRLDESCL3; /* LAYER[X].CTRLDESCL3 */ 03767 03768 union { 03769 vuint32_t R; 03770 struct { 03771 vuint32_t EN:1; 03772 vuint32_t TILEEN:1; 03773 vuint32_t DATASEL:1; 03774 vuint32_t:1; 03775 vuint32_t TRANS:8; 03776 vuint32_t BPP:4; 03777 vuint32_t SAFETYEN:1; 03778 vuint32_t:2; 03779 vuint32_t LUOFFS:10; 03780 vuint32_t BB:1; 03781 vuint32_t AB:2; 03782 } B; 03783 } CTRLDESCL4; /* LAYER[X].CTRLDESCL4 */ 03784 03785 union { 03786 vuint32_t R; 03787 struct { 03788 vuint32_t:8; 03789 vuint32_t CKMAXR:8; 03790 vuint32_t CKMAXG:8; 03791 vuint32_t CKMAXB:8; 03792 } B; 03793 } CTRLDESCL5; /* LAYER[X].CTRLDESCL5 */ 03794 03795 union { 03796 vuint32_t R; 03797 struct { 03798 vuint32_t:8; 03799 vuint32_t CKMINR:8; 03800 vuint32_t CKMING:8; 03801 vuint32_t CKMINB:8; 03802 } B; 03803 } CTRLDESCL6; /* LAYER[X].CTRLDESCL6 */ 03804 03805 union { 03806 vuint32_t R; 03807 struct { 03808 vuint32_t:4; 03809 vuint32_t TILEVERSIZE:12; 03810 vuint32_t:8; 03811 vuint32_t TILEHORSIZE:8; 03812 } B; 03813 } CTRLDESCL7; /* LAYER[X].CTRLDESCL7 */ 03814 03815 }; /* end of DCU_LAYER_tag */ 03816 03817 struct DCU_tag { 03818 03819 /* DCU.LAYER<[x]>.CTRLDESCL<y>.R {x = 0-15, y = 1-7} */ 03820 /* eg DCU.LAYER[0].CTRLDESCL1.R = 0; */ 03821 /* DCU.LAYER[0].CTRLDESCL1.B.HEIGHT = 0; */ 03822 struct DCU_LAYER_tag LAYER[16]; 03823 03824 union { 03825 vuint32_t R; 03826 struct { 03827 vuint32_t:8; 03828 vuint32_t HEIGHT:8; 03829 vuint32_t:8; 03830 vuint32_t WIDTH:8; 03831 } B; 03832 } CTRLDESCCURSOR1; /* Control Descriptor Cursor_1 Register */ 03833 03834 union { 03835 vuint32_t R; 03836 struct { 03837 vuint32_t:6; 03838 vuint32_t POSY:10; 03839 vuint32_t:6; 03840 vuint32_t POSX:10; 03841 } B; 03842 } CTRLDESCCURSOR2; /* Control Descriptor Cursor_2 Register */ 03843 03844 union { 03845 vuint32_t R; 03846 struct { 03847 vuint32_t CUREN:1; 03848 vuint32_t:7; 03849 vuint32_t CURSORDEFAULTCOLOR:24; 03850 } B; 03851 } CTRLDESCCURSOR3; /* Control Descriptor Cursor_3 Register */ 03852 03853 union { 03854 vuint32_t R; 03855 struct { 03856 vuint32_t:23; 03857 vuint32_t ENBLINK:1; 03858 vuint32_t HWCBLINK:8; 03859 } B; 03860 } CTRLDESCCURSOR4; /* Control Descriptor Cursor_4 Register */ 03861 03862 union { 03863 vuint32_t R; 03864 struct { 03865 vuint32_t DCUSWRST:1; 03866 vuint32_t:11; 03867 vuint32_t PDISYNCLOCK:4; 03868 vuint32_t:2; 03869 vuint32_t PDIEN:1; 03870 vuint32_t PDIBYTEREV:1; 03871 vuint32_t PDIDEMODE:1; 03872 vuint32_t PDINARROWMODE:1; 03873 vuint32_t PDI_MODE:2; 03874 vuint32_t PDISLAVEMODE:1; 03875 vuint32_t TAGEN:1; 03876 vuint32_t SIGEN:1; 03877 vuint32_t PDISYNC:1; 03878 vuint32_t TEST:1; 03879 vuint32_t ENGAMMA:1; 03880 vuint32_t DCUMODE:2; 03881 } B; 03882 } DCUMODE; /* DCU Mode Register */ 03883 03884 union { 03885 vuint32_t R; 03886 struct { 03887 vuint32_t:8; 03888 vuint32_t BGND_R:8; 03889 vuint32_t BGND_G:8; 03890 vuint32_t BGND_B:8; 03891 } B; 03892 } BGND; /* BGND Register */ 03893 03894 union { 03895 vuint32_t R; 03896 struct { 03897 vuint32_t:6; 03898 vuint32_t DELTAY:10; 03899 vuint32_t:8; 03900 vuint32_t DELTAX:8; 03901 } B; 03902 } DSPSIZE; /* DISP_SIZE Register */ 03903 03904 union { 03905 vuint32_t R; 03906 struct { 03907 vuint32_t:1; 03908 vuint32_t BPH:9; 03909 vuint32_t:2; 03910 vuint32_t PWH:9; 03911 vuint32_t:2; 03912 vuint32_t FPH:9; 03913 } B; 03914 } HSYNPARA; /* HSYNPARA Register */ 03915 03916 union { 03917 vuint32_t R; 03918 struct { 03919 vuint32_t:1; 03920 vuint32_t BPV:9; 03921 vuint32_t:2; 03922 vuint32_t PWV:9; 03923 vuint32_t:2; 03924 vuint32_t FPV:9; 03925 } B; 03926 } VSYNPARA; /* VSYNPARA Register */ 03927 03928 union { 03929 vuint32_t R; 03930 struct { 03931 vuint32_t:21; 03932 vuint32_t INVPDIDE:1; 03933 vuint32_t INVPDIHS:1; 03934 vuint32_t INVPDIVS:1; 03935 vuint32_t INVPDICLK:1; 03936 vuint32_t INVPXCK:1; 03937 vuint32_t NEG:1; 03938 vuint32_t BPVS:1; 03939 vuint32_t BPHS:1; 03940 vuint32_t INVCS:1; 03941 vuint32_t INVVS:1; 03942 vuint32_t INVHS:1; 03943 } B; 03944 } SYNPOL; /* SYNPOL Register */ 03945 03946 union { 03947 vuint32_t R; 03948 struct { 03949 vuint32_t:6; 03950 vuint32_t LSBFVS:10; 03951 vuint32_t OUTBUFHIGH:8; 03952 vuint32_t OUTBUFLOW:8; 03953 } B; 03954 } THRESHOLD; /* Threshold Register */ 03955 03956 union { 03957 vuint32_t R; 03958 struct { 03959 vuint32_t:20; 03960 vuint32_t IPMERROR:1; 03961 vuint32_t PROGEND:1; 03962 vuint32_t P2FIFOHIFLAG:1; 03963 vuint32_t P2FIFOLOFLAG:1; 03964 vuint32_t P1FIFOHIFLAG:1; 03965 vuint32_t P1FIFOLOFLAG:1; 03966 vuint32_t CRCOVERFLOW:1; 03967 vuint32_t CRCREADY:1; 03968 vuint32_t VSBLANK:1; 03969 vuint32_t LSBFVS:1; 03970 vuint32_t UNDRUN:1; 03971 vuint32_t VSYNC:1; 03972 } B; 03973 } INTSTATUS; /* Interrupt Status Register */ 03974 03975 union { 03976 vuint32_t R; 03977 struct { 03978 vuint32_t:20; 03979 vuint32_t MIPMERROR:1; 03980 vuint32_t MPROGEND:1; 03981 vuint32_t MP2FIFOHIFLAG:1; 03982 vuint32_t MP2FIFOLOFLAG:1; 03983 vuint32_t MP1FIFOHIFLAG:1; 03984 vuint32_t MP1FIFOLOFLAG:1; 03985 vuint32_t MCRCOVERFLOW:1; 03986 vuint32_t MCRCREADY:1; 03987 vuint32_t MVSBLANK:1; 03988 vuint32_t MLSBFVS:1; 03989 vuint32_t MUNDRUN:1; 03990 vuint32_t MVSYNC:1; 03991 } B; 03992 } INTMASK; /* Interrupt Mask Register */ 03993 03994 union { 03995 vuint32_t R; 03996 struct { 03997 vuint32_t:8; 03998 vuint32_t COLBAR_R:8; 03999 vuint32_t COLBAR_G:8; 04000 vuint32_t COLBAR_B:8; 04001 } B; 04002 } COLBAR[8]; /* COLBAR 1-8 Register */ 04003 04004 union { 04005 vuint32_t R; 04006 struct { 04007 vuint32_t:26; 04008 vuint32_t DIVRATIO:6; 04009 } B; 04010 } DIVRATIO; /* Clock Divider Register */ 04011 04012 union { 04013 vuint32_t R; 04014 struct { 04015 vuint32_t:6; 04016 vuint32_t SIGVERSIZE:10; 04017 vuint32_t:6; 04018 vuint32_t SIGHORSIZE:10; 04019 } B; 04020 } SIGNCALC1; 04021 04022 union { 04023 vuint32_t R; 04024 struct { 04025 vuint32_t:6; 04026 vuint32_t SIGVERSIZE:10; 04027 vuint32_t:6; 04028 vuint32_t SIGHORSIZE:10; 04029 } B; 04030 } SIGNCALC2; 04031 04032 union { 04033 vuint32_t R; 04034 struct { 04035 vuint32_t CRCVAL:32; 04036 } B; 04037 } CRCVAL; 04038 04039 union { 04040 vuint32_t R; 04041 struct { 04042 vuint32_t:22; 04043 vuint32_t PDIBLANKINGERR:1; 04044 vuint32_t PDIECCERR2:1; 04045 vuint32_t PDIECCERR1:1; 04046 vuint32_t PDILOCKLOST:1; 04047 vuint32_t PDILOCKDET:1; 04048 vuint32_t PDIVSYNCDET:1; 04049 vuint32_t PDIHSYNCDET:1; 04050 vuint32_t PDIDEDET:1; 04051 vuint32_t PDICLKLOST:1; 04052 vuint32_t PDICLKDET:1; 04053 } B; 04054 } PDISTATUS; /* PDI status Register */ 04055 04056 union { 04057 vuint32_t R; 04058 struct { 04059 vuint32_t:22; 04060 vuint32_t PDIBLANKINGERR:1; 04061 vuint32_t PDIECCERR2:1; 04062 vuint32_t PDIECCERR1:1; 04063 vuint32_t PDILOCKLOST:1; 04064 vuint32_t PDILOCKDET:1; 04065 vuint32_t PDIVSYNCDET:1; 04066 vuint32_t PDIHSYNCDET:1; 04067 vuint32_t PDIDEDET:1; 04068 vuint32_t PDICLKLOST:1; 04069 vuint32_t PDICLKDET:1; 04070 } B; 04071 } MASKPDISTATUS; /* PDI Status Mask Register */ 04072 04073 union { 04074 vuint32_t R; 04075 struct { 04076 vuint32_t:13; 04077 vuint32_t HWCERR:1; 04078 vuint32_t SIGERR:1; 04079 vuint32_t DISPERR:1; 04080 vuint32_t LPARERR:16; 04081 } B; 04082 } PARRERRSTATUS; 04083 04084 union { 04085 vuint32_t R; 04086 struct { 04087 vuint32_t:13; 04088 vuint32_t MHWCERR:1; 04089 vuint32_t MSIGERR:1; 04090 vuint32_t MDISPERR:1; 04091 vuint32_t MLPARERR:16; 04092 } B; 04093 } MASKPARRERRSTATUS; 04094 04095 union { 04096 vuint32_t R; 04097 struct { 04098 vuint32_t INPBUFP2HI:8; 04099 vuint32_t INPBUFP2LO:8; 04100 vuint32_t INPBUFP1HI:8; 04101 vuint32_t INPBUFP1LO:8; 04102 } B; 04103 } THRESHOLDINP; /* Threshold Input Buffer Register */ 04104 04105 vuint32_t DCU_reserved1[0x072]; /* Unused from end of registers */ 04106 04107 vuint32_t CURSOR[0x0100]; /* Hardware Cursor = 256 * 32bit */ 04108 04109 vuint32_t DCU_reserved2[0x200]; /* Unused = 512 * 32bit */ 04110 04111 vuint32_t CLUT[0x0400]; /* CLUT-Pallete memory = 1k * 32bit */ 04112 04113 vuint32_t TILE[0x0400]; /* Tile memory = 1k * 32bit */ 04114 04115 vuint32_t GAMMARED[0x100]; /* Gamma red table = 256 * 32bit */ 04116 04117 vuint32_t GAMMAGREEN[0x100]; /* Gamma green table = 256 * 32bit */ 04118 04119 vuint32_t GAMMABLUE[0x100]; /* Gamma blue table = 256 * 32bit */ 04120 04121 }; /* end of DCU_tag */ 04122 /****************************************************************************/ 04123 /* MODULE : CTUL */ 04124 /****************************************************************************/ 04125 struct CTUL_tag { 04126 union { 04127 vuint32_t R; 04128 struct { 04129 vuint32_t:16; 04130 vuint32_t PRESC_CONF:4; 04131 vuint32_t:4; 04132 vuint32_t TRGIEN:1; 04133 vuint32_t TRGI:1; 04134 vuint32_t:2; 04135 vuint32_t CNT3_EN:1; 04136 vuint32_t CNT2_EN:1; 04137 vuint32_t CNT1_EN:1; 04138 vuint32_t CNT0_EN:1; 04139 } B; 04140 } CSR; /* Control Status Register */ 04141 04142 union { 04143 vuint32_t R; 04144 struct { 04145 vuint32_t:23; 04146 vuint32_t SV:9; 04147 } B; 04148 } SVR[7]; /* Start Value Register */ 04149 04150 union { 04151 vuint32_t R; 04152 struct { 04153 vuint32_t:23; 04154 vuint32_t CV:9; 04155 } B; 04156 } CVR[4]; /* Current Value Register */ 04157 04158 union { 04159 vuint32_t R; 04160 struct { 04161 vuint32_t:16; 04162 vuint32_t TM:1; 04163 vuint32_t CNT:2; 04164 vuint32_t DELAY:3; 04165 vuint32_t:4; 04166 vuint32_t CHANNELVALUE:6; 04167 } B; 04168 } EVTCFGR[64]; /* Event Configuration Register */ 04169 04170 }; /* end of CTUL_tag */ 04171 /****************************************************************************/ 04172 /* MODULE : CTU */ 04173 /****************************************************************************/ 04174 struct CTU_tag { 04175 04176 union { 04177 vuint32_t R; 04178 struct { 04179 vuint32_t I15_FE:1; 04180 vuint32_t I15_RE:1; 04181 vuint32_t I14_FE:1; 04182 vuint32_t I14_RE:1; 04183 vuint32_t I13_FE:1; 04184 vuint32_t I13_RE:1; 04185 vuint32_t I12_FE:1; 04186 vuint32_t I12_RE:1; 04187 vuint32_t I11_FE:1; 04188 vuint32_t I11_RE:1; 04189 vuint32_t I10_FE:1; 04190 vuint32_t I10_RE:1; 04191 vuint32_t I9_FE:1; 04192 vuint32_t I9_RE:1; 04193 vuint32_t I8_FE:1; 04194 vuint32_t I8_RE:1; 04195 vuint32_t I7_FE:1; 04196 vuint32_t I7_RE:1; 04197 vuint32_t I6_FE:1; 04198 vuint32_t I6_RE:1; 04199 vuint32_t I5_FE:1; 04200 vuint32_t I5_RE:1; 04201 vuint32_t I4_FE:1; 04202 vuint32_t I4_RE:1; 04203 vuint32_t I3_FE:1; 04204 vuint32_t I3_RE:1; 04205 vuint32_t I2_FE:1; 04206 vuint32_t I2_RE:1; 04207 vuint32_t I1_FE:1; 04208 vuint32_t I1_RE:1; 04209 vuint32_t I0_FE:1; 04210 vuint32_t I0_RE:1; 04211 } B; 04212 } TGSISR; /* -Trigger Generator Subunit Input Selection Register */ 04213 04214 union { 04215 vuint16_t R; 04216 struct { 04217 vuint16_t:7; 04218 vuint16_t ETTM:1; 04219 vuint16_t PRES:2; 04220 vuint16_t MRSSM:5; 04221 vuint16_t TGSM:1; 04222 } B; 04223 } TGSCR; /* Trigger Generator Subunit Control Register */ 04224 04225 union { 04226 vuint16_t R; 04227 struct { 04228 vuint16_t TCRV:16; 04229 } B; 04230 } TCR[8]; /* Trigger 0->7 Compare Register */ 04231 04232 union { 04233 vuint16_t R; 04234 struct { 04235 vuint16_t TGSCCV:16; 04236 } B; 04237 } TGSCCR; /* TGS Counter Compare Register */ 04238 04239 union { 04240 vuint16_t R; 04241 struct { 04242 vuint16_t TGSCRV:16; 04243 } B; 04244 } TGSCRR; /* TGS Counter Reload Register */ 04245 04246 uint16_t CTU_reserved0; 04247 04248 union { 04249 vuint32_t R; 04250 struct { 04251 vuint32_t:3; 04252 vuint32_t T3INDEX:5; 04253 vuint32_t:3; 04254 vuint32_t T2INDEX:5; 04255 vuint32_t:3; 04256 vuint32_t T1INDEX:5; 04257 vuint32_t:3; 04258 vuint32_t T0INDEX:5; 04259 } B; 04260 } CLCR1; /* Command List Control Register 1 */ 04261 04262 union { 04263 vuint32_t R; 04264 struct { 04265 vuint32_t:3; 04266 vuint32_t T7INDEX:5; 04267 vuint32_t:3; 04268 vuint32_t T6INDEX:5; 04269 vuint32_t:3; 04270 vuint32_t T5INDEX:5; 04271 vuint32_t:3; 04272 vuint32_t T4INDEX:5; 04273 } B; 04274 } CLCR2; /* Command List Control Register 2 */ 04275 04276 union { 04277 vuint32_t R; 04278 struct { 04279 vuint32_t:3; 04280 vuint32_t T3E:1; 04281 vuint32_t T3ETE:1; 04282 vuint32_t T3T1E:1; 04283 vuint32_t T3T0E:1; 04284 vuint32_t T3ADCE:1; 04285 vuint32_t:3; 04286 vuint32_t T2E:1; 04287 vuint32_t T2ETE:1; 04288 vuint32_t T2T1E:1; 04289 vuint32_t T2T0E:1; 04290 vuint32_t T2ADCE:1; 04291 vuint32_t:3; 04292 vuint32_t T1E:1; 04293 vuint32_t T1ETE:1; 04294 vuint32_t T1T1E:1; 04295 vuint32_t T1T0E:1; 04296 vuint32_t T1ADCE:1; 04297 vuint32_t:3; 04298 vuint32_t T0E:1; 04299 vuint32_t T0ETE:1; 04300 vuint32_t T0T1E:1; 04301 vuint32_t T0T0E:1; 04302 vuint32_t T0ADCE:1; 04303 } B; 04304 } THCR1; /* Trigger Handler Control Register 1 */ 04305 04306 union { 04307 vuint32_t R; 04308 struct { 04309 vuint32_t:3; 04310 vuint32_t T7E:1; 04311 vuint32_t T7ETE:1; 04312 vuint32_t T7T1E:1; 04313 vuint32_t T7T0E:1; 04314 vuint32_t T7ADCE:1; 04315 vuint32_t:3; 04316 vuint32_t T6E:1; 04317 vuint32_t T6ETE:1; 04318 vuint32_t T6T1E:1; 04319 vuint32_t T6T0E:1; 04320 vuint32_t T6ADCE:1; 04321 vuint32_t:3; 04322 vuint32_t T5E:1; 04323 vuint32_t T5ETE:1; 04324 vuint32_t T5T1E:1; 04325 vuint32_t T5T0E:1; 04326 vuint32_t T5ADCE:1; 04327 vuint32_t:3; 04328 vuint32_t T4E:1; 04329 vuint32_t T4ETE:1; 04330 vuint32_t T4T1E:1; 04331 vuint32_t T4T0E:1; 04332 vuint32_t T4ADCE:1; 04333 } B; 04334 } THCR2; /* Trigger Handler Control Register 2 */ 04335 04336 /* Single Conversion Mode - Comment for Dual Conversion Mode */ 04337 union { 04338 vuint16_t R; 04339 struct { 04340 vuint16_t CIR:1; 04341 vuint16_t LC:1; 04342 vuint16_t CMS:1; 04343 vuint16_t FIFO:3; 04344 vuint16_t:1; 04345 vuint16_t:3; 04346 vuint16_t SU:1; 04347 vuint16_t:1; 04348 vuint16_t CH:4; 04349 } B; 04350 } CLR[32]; /* Commands List Register x (double-buffered) (x = 1,...,32) */ 04351 04352 /* Uncomment for Dual Conversion Mode */ 04353 /*union { 04354 vuint16_t R; 04355 struct { 04356 vuint16_t CIR:1; 04357 vuint16_t LC:1; 04358 vuint16_t CMS:1; 04359 vuint16_t FIFO:3; 04360 vuint16_t :1; 04361 vuint16_t CHB:4; 04362 vuint16_t :1; 04363 vuint16_t CHA:4; 04364 } B; 04365 } CLR[32]; */ 04366 /* Commands List Register x (double-buffered) (x = 1,...,32) */ 04367 04368 union { 04369 vuint16_t R; 04370 struct { 04371 vuint16_t:8; 04372 vuint16_t DMAEN7:1; 04373 vuint16_t DMAEN6:1; 04374 vuint16_t DMAEN5:1; 04375 vuint16_t DMAEN4:1; 04376 vuint16_t DMAEN3:1; 04377 vuint16_t DMAEN2:1; 04378 vuint16_t DMAEN1:1; 04379 vuint16_t DMAEN0:1; 04380 } B; 04381 } CR; /* Control Register */ 04382 04383 union { 04384 vuint32_t R; 04385 struct { 04386 vuint32_t FIFO_OVERRUN_EN7:1; 04387 vuint32_t FIFO_OVERFLOW_EN7:1; 04388 vuint32_t FIFO_EMPTY_EN7:1; 04389 vuint32_t FIFO_FULL_EN7:1; 04390 vuint32_t FIFO_OVERRUN_EN6:1; 04391 vuint32_t FIFO_OVERFLOW_EN6:1; 04392 vuint32_t FIFO_EMPTY_EN6:1; 04393 vuint32_t FIFO_FULL_EN6:1; 04394 vuint32_t FIFO_OVERRUN_EN5:1; 04395 vuint32_t FIFO_OVERFLOW_EN5:1; 04396 vuint32_t FIFO_EMPTY_EN5:1; 04397 vuint32_t FIFO_FULL_EN5:1; 04398 vuint32_t FIFO_OVERRUN_EN4:1; 04399 vuint32_t FIFO_OVERFLOW_EN4:1; 04400 vuint32_t FIFO_EMPTY_EN4:1; 04401 vuint32_t FIFO_FULL_EN4:1; 04402 vuint32_t FIFO_OVERRUN_EN3:1; 04403 vuint32_t FIFO_OVERFLOW_EN3:1; 04404 vuint32_t FIFO_EMPTY_EN3:1; 04405 vuint32_t FIFO_FULL_EN3:1; 04406 vuint32_t FIFO_OVERRUN_EN2:1; 04407 vuint32_t FIFO_OVERFLOW_EN2:1; 04408 vuint32_t FIFO_EMPTY_EN2:1; 04409 vuint32_t FIFO_FULL_EN2:1; 04410 vuint32_t FIFO_OVERRUN_EN1:1; 04411 vuint32_t FIFO_OVERFLOW_EN1:1; 04412 vuint32_t FIFO_EMPTY_EN1:1; 04413 vuint32_t FIFO_FULL_EN1:1; 04414 vuint32_t FIFO_OVERRUN_EN0:1; 04415 vuint32_t FIFO_OVERFLOW_EN0:1; 04416 vuint32_t FIFO_EMPTY_EN0:1; 04417 vuint32_t FIFO_FULL_EN0:1; 04418 } B; 04419 } FCR; /* CONTROL REGISTER FIFO */ 04420 04421 union { 04422 vuint32_t R; 04423 struct { 04424 vuint32_t THRESHOLD3:8; 04425 vuint32_t THRESHOLD2:8; 04426 vuint32_t THRESHOLD1:8; 04427 vuint32_t THRESHOLD0:8; 04428 } B; 04429 } TH1; /* Threshold Register */ 04430 04431 union { 04432 vuint32_t R; 04433 struct { 04434 vuint32_t THRESHOLD7:8; 04435 vuint32_t THRESHOLD6:8; 04436 vuint32_t THRESHOLD5:8; 04437 vuint32_t THRESHOLD4:8; 04438 } B; 04439 } TH2; /* Threshold Register */ 04440 04441 union { 04442 vuint32_t R; 04443 struct { 04444 vuint32_t FIFO_OVERRUN7:1; 04445 vuint32_t FIFO_OVERFLOW7:1; 04446 vuint32_t FIFO_EMPTY7:1; 04447 vuint32_t FIFO_FULL7:1; 04448 vuint32_t FIFO_OVERRUN6:1; 04449 vuint32_t FIFO_OVERFLOW6:1; 04450 vuint32_t FIFO_EMPTY6:1; 04451 vuint32_t FIFO_FULL6:1; 04452 vuint32_t FIFO_OVERRUN5:1; 04453 vuint32_t FIFO_OVERFLOW5:1; 04454 vuint32_t FIFO_EMPTY5:1; 04455 vuint32_t FIFO_FULL5:1; 04456 vuint32_t FIFO_OVERRUN4:1; 04457 vuint32_t FIFO_OVERFLOW4:1; 04458 vuint32_t FIFO_EMPTY4:1; 04459 vuint32_t FIFO_FULL4:1; 04460 vuint32_t FIFO_OVERRUN3:1; 04461 vuint32_t FIFO_OVERFLOW3:1; 04462 vuint32_t FIFO_EMPTY3:1; 04463 vuint32_t FIFO_FULL3:1; 04464 vuint32_t FIFO_OVERRUN2:1; 04465 vuint32_t FIFO_OVERFLOW2:1; 04466 vuint32_t FIFO_EMPTY2:1; 04467 vuint32_t FIFO_FULL2:1; 04468 vuint32_t FIFO_OVERRUN1:1; 04469 vuint32_t FIFO_OVERFLOW1:1; 04470 vuint32_t FIFO_EMPTY1:1; 04471 vuint32_t FIFO_FULL1:1; 04472 vuint32_t FIFO_OVERRUN0:1; 04473 vuint32_t FIFO_OVERFLOW0:1; 04474 vuint32_t FIFO_EMPTY0:1; 04475 vuint32_t FIFO_FULL0:1; 04476 } B; 04477 } STATUS; /* STATUS REGISTER */ 04478 04479 union { 04480 vuint32_t R; 04481 struct { 04482 vuint32_t:11; 04483 vuint32_t NCH:5; 04484 vuint32_t:6; 04485 vuint32_t DATA:10; 04486 } B; 04487 } FRA[8]; /* FIFO RIGHT aligned REGISTER */ 04488 04489 union { 04490 vuint32_t R; 04491 struct { 04492 vuint32_t:11; 04493 vuint32_t NCH:5; 04494 vuint32_t DATA:10; 04495 vuint32_t:6; 04496 } B; 04497 } FLA[8]; /* FIFO LEFT aligned REGISTER */ 04498 04499 union { 04500 vuint16_t R; 04501 struct { 04502 vuint16_t:7; 04503 vuint16_t ETOE:1; 04504 vuint16_t T1OE:1; 04505 vuint16_t T0OE:1; 04506 vuint16_t ADCOE:1; 04507 vuint16_t TGSOSM:1; 04508 vuint16_t MRSO:1; 04509 vuint16_t ICE:1; 04510 vuint16_t SMTO:1; 04511 vuint16_t MRSRE:1; 04512 } B; 04513 } CTUEFR; /* Cross Triggering Unit Error Flag Register */ 04514 04515 union { 04516 vuint16_t R; 04517 struct { 04518 vuint16_t:6; 04519 vuint16_t ADC:1; 04520 vuint16_t T7:1; 04521 vuint16_t T6:1; 04522 vuint16_t T5:1; 04523 vuint16_t T4:1; 04524 vuint16_t T3:1; 04525 vuint16_t T2:1; 04526 vuint16_t T1:1; 04527 vuint16_t T0:1; 04528 vuint16_t MRS:1; 04529 } B; 04530 } CTUIFR; /* Cross Triggering Unit Interrupt Flag Register */ 04531 04532 union { 04533 vuint16_t R; 04534 struct { 04535 vuint16_t T7IE:1; 04536 vuint16_t T6IE:1; 04537 vuint16_t T5IE:1; 04538 vuint16_t T4IE:1; 04539 vuint16_t T3IE:1; 04540 vuint16_t T2IE:1; 04541 vuint16_t T1IE:1; 04542 vuint16_t T0IE:1; 04543 vuint16_t:5; 04544 vuint16_t MRSDMAE:1; 04545 vuint16_t MRSIE:1; 04546 vuint16_t IEE:1; 04547 } B; 04548 } CTUIR; /* Cross Triggering Unit Interrupt/DMA Register */ 04549 04550 union { 04551 vuint16_t R; 04552 struct { 04553 vuint16_t:8; 04554 vuint16_t COTR:8; 04555 } B; 04556 } COTR; /* Control On-Time Register */ 04557 04558 union { 04559 vuint16_t R; 04560 struct { 04561 vuint16_t T7SG:1; 04562 vuint16_t T6SG:1; 04563 vuint16_t T5SG:1; 04564 vuint16_t T4SG:1; 04565 vuint16_t T3SG:1; 04566 vuint16_t T2SG:1; 04567 vuint16_t T1SG:1; 04568 vuint16_t T0SG:1; 04569 vuint16_t CTUADCRESET:1; 04570 vuint16_t CTUODIS:1; 04571 vuint16_t FILTERENABLE:1; 04572 vuint16_t CGRE:1; 04573 vuint16_t FGRE:1; 04574 vuint16_t MRSSG:1; 04575 vuint16_t GRE:1; 04576 vuint16_t TGSISRRE:1; 04577 } B; 04578 } CTUCR; /* Cross Triggering Unit Control Register */ 04579 04580 union { 04581 vuint16_t R; 04582 struct { 04583 vuint16_t:8; 04584 vuint16_t FILTERVALUE:8; 04585 } B; 04586 } CTUFILTER; /* Cross Triggering Unit Digital Filter */ 04587 04588 union { 04589 vuint16_t R; 04590 struct { 04591 vuint16_t:15; 04592 vuint16_t MDIS:1; 04593 } B; 04594 } CTUPCR; /* Cross Triggering Unit Power Control */ 04595 04596 }; /* end of CTU_tag */ 04597 /****************************************************************************/ 04598 /* MODULE : FCU */ 04599 /****************************************************************************/ 04600 struct FCU_tag { 04601 04602 union { 04603 vuint32_t R; 04604 struct { 04605 vuint32_t MCL:1; 04606 vuint32_t TM:2; 04607 vuint32_t:19; 04608 vuint32_t PS:2; 04609 vuint32_t FOM:2; 04610 vuint32_t FOP:6; 04611 } B; 04612 } MCR; /* Module Configuration Register */ 04613 04614 union { 04615 vuint32_t R; 04616 struct { 04617 vuint32_t SRF0:1; 04618 vuint32_t SRF1:1; 04619 vuint32_t SRF2:1; 04620 vuint32_t SRF3:1; 04621 vuint32_t SRF4:1; 04622 vuint32_t SRF5:1; 04623 vuint32_t SRF6:1; 04624 vuint32_t SRF7:1; 04625 vuint32_t SRF8:1; 04626 vuint32_t SRF9:1; 04627 vuint32_t SRF10:1; 04628 vuint32_t SRF11:1; 04629 vuint32_t SRF12:1; 04630 vuint32_t SRF13:1; 04631 vuint32_t SRF14:1; 04632 vuint32_t SRF15:1; 04633 vuint32_t HRF15:1; 04634 vuint32_t HRF14:1; 04635 vuint32_t HRF13:1; 04636 vuint32_t HRF12:1; 04637 vuint32_t HRF11:1; 04638 vuint32_t HRF10:1; 04639 vuint32_t HRF9:1; 04640 vuint32_t HRF8:1; 04641 vuint32_t HRF7:1; 04642 vuint32_t HRF6:1; 04643 vuint32_t HRF5:1; 04644 vuint32_t HRF4:1; 04645 vuint32_t HRF3:1; 04646 vuint32_t HRF2:1; 04647 vuint32_t HRF1:1; 04648 vuint32_t HRF0:1; 04649 } B; 04650 } FFR; /* Fault Flag Register */ 04651 04652 union { 04653 vuint32_t R; 04654 struct { 04655 vuint32_t FRSRF0:1; 04656 vuint32_t FRSRF1:1; 04657 vuint32_t FRSRF2:1; 04658 vuint32_t FRSRF3:1; 04659 vuint32_t FRSRF4:1; 04660 vuint32_t FRSRF5:1; 04661 vuint32_t FRSRF6:1; 04662 vuint32_t FRSRF7:1; 04663 vuint32_t FRSRF8:1; 04664 vuint32_t FRSRF9:1; 04665 vuint32_t FRSRF10:1; 04666 vuint32_t FRSRF11:1; 04667 vuint32_t FRSRF12:1; 04668 vuint32_t FRSRF13:1; 04669 vuint32_t FRSRF14:1; 04670 vuint32_t FRSRF15:1; 04671 vuint32_t FRHRF15:1; 04672 vuint32_t FRHRF14:1; 04673 vuint32_t FRHRF13:1; 04674 vuint32_t FRHRF12:1; 04675 vuint32_t FRHRF11:1; 04676 vuint32_t FRHRF10:1; 04677 vuint32_t FRHRF9:1; 04678 vuint32_t FRHRF8:1; 04679 vuint32_t FRHRF7:1; 04680 vuint32_t FRHRF6:1; 04681 vuint32_t FRHRF5:1; 04682 vuint32_t FRHRF4:1; 04683 vuint32_t FRHRF3:1; 04684 vuint32_t FRHRF2:1; 04685 vuint32_t FRHRF1:1; 04686 vuint32_t FRHRF0:1; 04687 } B; 04688 } FFFR; /* Frozen Fault Flag Register */ 04689 04690 union { 04691 vuint32_t R; 04692 struct { 04693 vuint32_t:2; 04694 vuint32_t FSRF2:1; 04695 vuint32_t FSRF3:1; 04696 vuint32_t FSRF4:1; 04697 vuint32_t FSRF5:1; 04698 vuint32_t FSRF6:1; 04699 vuint32_t FSRF7:1; 04700 vuint32_t FSRF8:1; 04701 vuint32_t FSRF9:1; 04702 vuint32_t FSRF10:1; 04703 vuint32_t FSRF11:1; 04704 vuint32_t FSRF12:1; 04705 vuint32_t FSRF13:1; 04706 vuint32_t FSRF14:1; 04707 vuint32_t FSRF15:1; 04708 vuint32_t FHRF15:1; 04709 vuint32_t FHRF14:1; 04710 vuint32_t FHRF13:1; 04711 vuint32_t FHRF12:1; 04712 vuint32_t FHRF11:1; 04713 vuint32_t FHRF10:1; 04714 vuint32_t FHRF9:1; 04715 vuint32_t FHRF8:1; 04716 vuint32_t FHRF7:1; 04717 vuint32_t FHRF6:1; 04718 vuint32_t FHRF5:1; 04719 vuint32_t FHRF4:1; 04720 vuint32_t FHRF3:1; 04721 vuint32_t FHRF2:1; 04722 vuint32_t FHRF1:1; 04723 vuint32_t FHRF0:1; 04724 } B; 04725 } FFGR; /* Fake Fault Generation Register */ 04726 04727 union { 04728 vuint32_t R; 04729 struct { 04730 vuint32_t ESF0:1; 04731 vuint32_t ESF1:1; 04732 vuint32_t ESF2:1; 04733 vuint32_t ESF3:1; 04734 vuint32_t ESF4:1; 04735 vuint32_t ESF5:1; 04736 vuint32_t ESF6:1; 04737 vuint32_t ESF7:1; 04738 vuint32_t ESF8:1; 04739 vuint32_t ESF9:1; 04740 vuint32_t ESF10:1; 04741 vuint32_t ESF11:1; 04742 vuint32_t ESF12:1; 04743 vuint32_t ESF13:1; 04744 vuint32_t ESF14:1; 04745 vuint32_t ESF15:1; 04746 vuint32_t EHF15:1; 04747 vuint32_t EHF14:1; 04748 vuint32_t EHF13:1; 04749 vuint32_t EHF12:1; 04750 vuint32_t EHF11:1; 04751 vuint32_t EHF10:1; 04752 vuint32_t EHF9:1; 04753 vuint32_t EHF8:1; 04754 vuint32_t EHF7:1; 04755 vuint32_t EHF6:1; 04756 vuint32_t EHF5:1; 04757 vuint32_t EHF4:1; 04758 vuint32_t EHF3:1; 04759 vuint32_t EHF2:1; 04760 vuint32_t EHF1:1; 04761 vuint32_t EHF0:1; 04762 } B; 04763 } FER; /* Fault Enable Register */ 04764 04765 union { 04766 vuint32_t R; 04767 struct { 04768 vuint32_t KR:32; 04769 } B; 04770 } KR; /* Fault Collection Unit Key Register */ 04771 04772 union { 04773 vuint32_t R; 04774 struct { 04775 vuint32_t TR:32; 04776 } B; 04777 } TR; /* Fault Collection Unit Timeout Register */ 04778 04779 union { 04780 vuint32_t R; 04781 struct { 04782 vuint32_t TESF0:1; 04783 vuint32_t TESF1:1; 04784 vuint32_t TESF2:1; 04785 vuint32_t TESF3:1; 04786 vuint32_t TESF4:1; 04787 vuint32_t TESF5:1; 04788 vuint32_t TESF6:1; 04789 vuint32_t TESF7:1; 04790 vuint32_t TESF8:1; 04791 vuint32_t TESF9:1; 04792 vuint32_t TESF10:1; 04793 vuint32_t TESF11:1; 04794 vuint32_t TESF12:1; 04795 vuint32_t TESF13:1; 04796 vuint32_t TESF14:1; 04797 vuint32_t TESF15:1; 04798 vuint32_t TEHF15:1; 04799 vuint32_t TEHF14:1; 04800 vuint32_t TEHF13:1; 04801 vuint32_t TEHF12:1; 04802 vuint32_t TEHF11:1; 04803 vuint32_t TEHF10:1; 04804 vuint32_t TEHF9:1; 04805 vuint32_t TEHF8:1; 04806 vuint32_t TEHF7:1; 04807 vuint32_t TEHF6:1; 04808 vuint32_t TEHF5:1; 04809 vuint32_t TEHF4:1; 04810 vuint32_t TEHF3:1; 04811 vuint32_t TEHF2:1; 04812 vuint32_t TEHF1:1; 04813 vuint32_t TEHF0:1; 04814 } B; 04815 } TER; /* Fault Collection Unit Timeout Enable Register */ 04816 04817 union { 04818 vuint32_t R; 04819 struct { 04820 vuint32_t:28; 04821 vuint32_t S0:1; 04822 vuint32_t S1:1; 04823 vuint32_t S2:1; 04824 vuint32_t S3:1; 04825 } B; 04826 } MSR; /* Module state register */ 04827 04828 union { 04829 vuint32_t R; 04830 struct { 04831 vuint32_t:12; 04832 vuint32_t MCPS:4; 04833 vuint32_t:12; 04834 vuint32_t MCAS:4; 04835 } B; 04836 } MCSR; /* MC state register */ 04837 04838 union { 04839 vuint32_t R; 04840 struct { 04841 vuint32_t:12; 04842 vuint32_t FRMCPS:4; 04843 vuint32_t:12; 04844 vuint32_t FRMCAS:4; 04845 } B; 04846 } FMCSR; /* Frozen MC State Register */ 04847 04848 }; /* end of FCU_tag */ 04849 /****************************************************************************/ 04850 /* MODULE : SMC - Stepper Motor Control */ 04851 /****************************************************************************/ 04852 struct SMC_tag { 04853 04854 union { 04855 vuint8_t R; 04856 struct { 04857 vuint8_t:1; 04858 vuint8_t MCPRE:2; 04859 vuint8_t MCSWAI:1; 04860 vuint8_t:1; 04861 vuint8_t DITH:1; 04862 vuint8_t:1; 04863 vuint8_t MCTOIF:1; 04864 } B; 04865 } CTL0; /* Motor Controller Control Register 0 */ 04866 04867 union { 04868 vuint8_t R; 04869 struct { 04870 vuint8_t RECIRC:1; 04871 vuint8_t:6; 04872 vuint8_t MCTOIE:1; 04873 } B; 04874 } CTL1; /* Motor Controller Control Register 1 */ 04875 04876 union { 04877 vuint16_t R; 04878 struct { 04879 vuint16_t:5; 04880 vuint16_t P:11; 04881 } B; 04882 } PER; /* Motor Controller Period Register */ 04883 04884 int32_t SMC_reserved0[3]; /* (0x010 - 0x004)/4 = 0x01 */ 04885 04886 union { 04887 vuint8_t R; 04888 struct { 04889 vuint8_t MCOM:2; 04890 vuint8_t MCAM:2; 04891 vuint8_t:2; 04892 vuint8_t CD:2; 04893 } B; 04894 } CC[12]; /* Motor Controller Channel Control Register 0->11 */ 04895 04896 int32_t SMC_reserved1; /* (0x020 - 0x01C)/4 = 0x01 */ 04897 04898 union { 04899 vuint16_t R; 04900 struct { 04901 vuint16_t S:5; 04902 vuint16_t D:11; 04903 } B; 04904 } DC[12]; /* Motor Controller Duty Cycle Register 0->11 */ 04905 04906 int8_t SMC_reserved2[8]; /* (0x040 - 0x038) = 0x08 */ 04907 04908 union { 04909 vuint8_t R; 04910 struct { 04911 vuint8_t TOUT:8; 04912 } B; 04913 } SDTO; /* Shortcut detector time-out register */ 04914 04915 int8_t SMC_reserved3[3]; /* (0x044 - 0x041) = 0x03 */ 04916 04917 union { 04918 vuint8_t R; 04919 struct { 04920 vuint8_t EN:8; 04921 } B; 04922 } SDE[3]; /* Shortcut detector enable register 0->2 */ 04923 04924 int8_t SMC_reserved4; /* (0x048 - 0x047) = 0x01 */ 04925 04926 union { 04927 vuint8_t R; 04928 struct { 04929 vuint8_t IRQ_EN:8; 04930 } B; 04931 } SDIEN[3]; /* Shortcut detector interrupt enable register 0->2 */ 04932 04933 int8_t SMC_reserved5; /* (0x04C - 0x04B) = 0x01 */ 04934 04935 union { 04936 vuint8_t R; 04937 struct { 04938 vuint8_t IRQ:8; 04939 } B; 04940 } SDI[3]; /* Shortcut detector interrupt register 0->2 */ 04941 04942 }; /* end of SMC_tag */ 04943 /****************************************************************************/ 04944 /* MODULE : SSD - Stepper Stall Detect */ 04945 /****************************************************************************/ 04946 struct SSD_tag { 04947 04948 union { 04949 vuint16_t R; 04950 struct { 04951 vuint16_t TRIG:1; 04952 vuint16_t STEP:2; 04953 vuint16_t RCIR:1; 04954 vuint16_t ITGDIR:1; 04955 vuint16_t BLNDCL:1; 04956 vuint16_t ITGDCL:1; 04957 vuint16_t RTZE:1; 04958 vuint16_t:1; 04959 vuint16_t BLNST:1; 04960 vuint16_t ITGST:1; 04961 vuint16_t:3; 04962 vuint16_t SDCPU:1; 04963 vuint16_t DZDIS:1; 04964 } B; 04965 } CONTROL; /* Control & Status Register */ 04966 04967 union { 04968 vuint16_t R; 04969 struct { 04970 vuint16_t BLNIF:1; 04971 vuint16_t ITGIF:1; 04972 vuint16_t:5; 04973 vuint16_t ACOVIF:1; 04974 vuint16_t BLNIE:1; 04975 vuint16_t ITGIE:1; 04976 vuint16_t:5; 04977 vuint16_t ACOVIE:1; 04978 } B; 04979 } IRQ; /* Interrupt Flag and Enable Register */ 04980 04981 union { 04982 vuint16_t R; 04983 struct { 04984 vuint16_t ITGACC:16; 04985 } B; 04986 } ITGACC; /* Integrator Accumulator register */ 04987 04988 union { 04989 vuint16_t R; 04990 struct { 04991 vuint16_t DCNT:16; 04992 } B; 04993 } DCNT; /* Down Counter Count register */ 04994 04995 union { 04996 vuint16_t R; 04997 struct { 04998 vuint16_t BLNCNTLD:16; 04999 } B; 05000 } BLNCNTLD; /* Blanking Counter Load register */ 05001 05002 union { 05003 vuint16_t R; 05004 struct { 05005 vuint16_t ITGCNTLD:16; 05006 } B; 05007 } ITGCNTLD; /* Integration Counter Load register */ 05008 05009 union { 05010 vuint16_t R; 05011 struct { 05012 vuint16_t:1; 05013 vuint16_t BLNDIV:3; 05014 vuint16_t:1; 05015 vuint16_t ITSSDIV:3; 05016 vuint16_t:2; 05017 vuint16_t OFFCNC:2; 05018 vuint16_t:1; 05019 vuint16_t ACDIV:3; 05020 } B; 05021 } PRESCALE; /* Prescaler register */ 05022 05023 union { 05024 vuint16_t R; 05025 struct { 05026 vuint16_t TMST:1; 05027 vuint16_t ANLOUT:1; 05028 vuint16_t ANLIN:1; 05029 vuint16_t SSDEN:1; 05030 vuint16_t STEP1:1; 05031 vuint16_t POL:1; 05032 vuint16_t ITG:1; 05033 vuint16_t DACHIZ:1; 05034 vuint16_t BUFHIZ:1; 05035 vuint16_t AMPHIZ:1; 05036 vuint16_t RESSHORT:1; 05037 vuint16_t ITSSDRV:1; 05038 vuint16_t ITSSDRVEN:1; 05039 vuint16_t REFDRV:1; 05040 vuint16_t REFDRVEN:1; 05041 } B; 05042 } FNTEST; /* Functional Test Mode register */ 05043 05044 }; /* end of SSD_tag */ 05045 /****************************************************************************/ 05046 /* MODULE : EMIOS */ 05047 /****************************************************************************/ 05048 struct EMIOS_CHANNEL_tag { 05049 union { 05050 vuint32_t R; 05051 struct { 05052 vuint32_t:8; 05053 vuint32_t CADR:24; 05054 } B; 05055 } CADR; /* Channel A Data Register */ 05056 05057 union { 05058 vuint32_t R; 05059 struct { 05060 vuint32_t:8; 05061 vuint32_t CBDR:24; 05062 } B; 05063 } CBDR; /* Channel B Data Register */ 05064 05065 union { 05066 vuint32_t R; 05067 struct { 05068 vuint32_t:8; 05069 vuint32_t CCNTR:24; 05070 } B; 05071 } CCNTR; /* Channel Counter Register */ 05072 05073 union { 05074 vuint32_t R; 05075 struct { 05076 vuint32_t FREN:1; 05077 vuint32_t ODIS:1; 05078 vuint32_t ODISSL:2; 05079 vuint32_t UCPRE:2; 05080 vuint32_t UCPEN:1; 05081 vuint32_t DMA:1; 05082 vuint32_t:1; 05083 vuint32_t IF:4; 05084 vuint32_t FCK:1; 05085 vuint32_t FEN:1; 05086 vuint32_t:3; 05087 vuint32_t FORCMA:1; 05088 vuint32_t FORCMB:1; 05089 vuint32_t:1; 05090 vuint32_t BSL:2; 05091 vuint32_t EDSEL:1; 05092 vuint32_t EDPOL:1; 05093 vuint32_t MODE:7; 05094 } B; 05095 } CCR; /* Channel Control Register */ 05096 05097 union { 05098 vuint32_t R; 05099 struct { 05100 vuint32_t OVR:1; 05101 vuint32_t:15; 05102 vuint32_t OVFL:1; 05103 vuint32_t:12; 05104 vuint32_t UCIN:1; 05105 vuint32_t UCOUT:1; 05106 vuint32_t FLAG:1; 05107 } B; 05108 } CSR; /* Channel Status Register */ 05109 05110 union { 05111 vuint32_t R; /* Alternate Channel A Data Register */ 05112 } ALTCADR; 05113 05114 uint32_t emios_channel_reserved[2]; 05115 05116 }; /* end of EMIOS_CHANNEL_tag */ 05117 05118 struct EMIOS_tag { 05119 union { 05120 vuint32_t R; 05121 struct { 05122 vuint32_t:1; 05123 vuint32_t MDIS:1; 05124 vuint32_t FRZ:1; 05125 vuint32_t GTBE:1; 05126 vuint32_t ETB:1; 05127 vuint32_t GPREN:1; 05128 vuint32_t:6; 05129 vuint32_t SRV:4; 05130 vuint32_t GPRE:8; 05131 vuint32_t:8; 05132 } B; 05133 } MCR; /* Module Configuration Register */ 05134 05135 union { 05136 vuint32_t R; 05137 struct { 05138 vuint32_t:8; 05139 vuint32_t F23:1; 05140 vuint32_t F22:1; 05141 vuint32_t F21:1; 05142 vuint32_t F20:1; 05143 vuint32_t F19:1; 05144 vuint32_t F18:1; 05145 vuint32_t F17:1; 05146 vuint32_t F16:1; 05147 vuint32_t F15:1; 05148 vuint32_t F14:1; 05149 vuint32_t F13:1; 05150 vuint32_t F12:1; 05151 vuint32_t F11:1; 05152 vuint32_t F10:1; 05153 vuint32_t F9:1; 05154 vuint32_t F8:1; 05155 vuint32_t F7:1; 05156 vuint32_t F6:1; 05157 vuint32_t F5:1; 05158 vuint32_t F4:1; 05159 vuint32_t F3:1; 05160 vuint32_t F2:1; 05161 vuint32_t F1:1; 05162 vuint32_t F0:1; 05163 } B; 05164 } GFR; /* Global FLAG Register */ 05165 05166 union { 05167 vuint32_t R; 05168 struct { 05169 vuint32_t:8; 05170 vuint32_t OU23:1; 05171 vuint32_t OU22:1; 05172 vuint32_t OU21:1; 05173 vuint32_t OU20:1; 05174 vuint32_t OU19:1; 05175 vuint32_t OU18:1; 05176 vuint32_t OU17:1; 05177 vuint32_t OU16:1; 05178 vuint32_t OU15:1; 05179 vuint32_t OU14:1; 05180 vuint32_t OU13:1; 05181 vuint32_t OU12:1; 05182 vuint32_t OU11:1; 05183 vuint32_t OU10:1; 05184 vuint32_t OU9:1; 05185 vuint32_t OU8:1; 05186 vuint32_t OU7:1; 05187 vuint32_t OU6:1; 05188 vuint32_t OU5:1; 05189 vuint32_t OU4:1; 05190 vuint32_t OU3:1; 05191 vuint32_t OU2:1; 05192 vuint32_t OU1:1; 05193 vuint32_t OU0:1; 05194 } B; 05195 } OUDR; /* Output Update Disable Register */ 05196 05197 union { 05198 vuint32_t R; 05199 struct { 05200 vuint32_t:8; 05201 vuint32_t CHDIS23:1; 05202 vuint32_t CHDIS22:1; 05203 vuint32_t CHDIS21:1; 05204 vuint32_t CHDIS20:1; 05205 vuint32_t CHDIS19:1; 05206 vuint32_t CHDIS18:1; 05207 vuint32_t CHDIS17:1; 05208 vuint32_t CHDIS16:1; 05209 vuint32_t CHDIS15:1; 05210 vuint32_t CHDIS14:1; 05211 vuint32_t CHDIS13:1; 05212 vuint32_t CHDIS12:1; 05213 vuint32_t CHDIS11:1; 05214 vuint32_t CHDIS10:1; 05215 vuint32_t CHDIS9:1; 05216 vuint32_t CHDIS8:1; 05217 vuint32_t CHDIS7:1; 05218 vuint32_t CHDIS6:1; 05219 vuint32_t CHDIS5:1; 05220 vuint32_t CHDIS4:1; 05221 vuint32_t CHDIS3:1; 05222 vuint32_t CHDIS2:1; 05223 vuint32_t CHDIS1:1; 05224 vuint32_t CHDIS0:1; 05225 } B; 05226 } UCDIS; /* Disable Channel Register */ 05227 05228 uint32_t emios_reserved1[4]; 05229 05230 struct EMIOS_CHANNEL_tag CH[28]; 05231 05232 }; /* end of EMIOS_tag */ 05233 /****************************************************************************/ 05234 /* MODULE : pit */ 05235 /****************************************************************************/ 05236 struct PIT_tag { 05237 union { 05238 vuint32_t R; 05239 struct { 05240 vuint32_t:30; 05241 vuint32_t MDIS:1; 05242 vuint32_t FRZ:1; 05243 } B; 05244 } PITMCR; 05245 05246 uint32_t pit_reserved1[63]; /* (0x0100 - 0x0004)/4 = 0x3F */ 05247 05248 struct { 05249 union { 05250 vuint32_t R; 05251 struct { 05252 vuint32_t TSV:32; 05253 } B; 05254 } LDVAL; 05255 05256 union { 05257 vuint32_t R; 05258 struct { 05259 vuint32_t TVL:32; 05260 } B; 05261 } CVAL; 05262 05263 union { 05264 vuint32_t R; 05265 struct { 05266 vuint32_t:30; 05267 vuint32_t TIE:1; 05268 vuint32_t TEN:1; 05269 } B; 05270 } TCTRL; 05271 05272 union { 05273 vuint32_t R; 05274 struct { 05275 vuint32_t:31; 05276 vuint32_t TIF:1; 05277 } B; 05278 } TFLG; 05279 } CH[6]; 05280 05281 }; /* end of PIT_tag */ 05282 /****************************************************************************/ 05283 /* MODULE : i2c */ 05284 /****************************************************************************/ 05285 struct I2C_tag { 05286 union { 05287 vuint8_t R; 05288 struct { 05289 vuint8_t ADR:7; 05290 vuint8_t:1; 05291 } B; 05292 } IBAD; /* Module Bus Address Register */ 05293 05294 union { 05295 vuint8_t R; 05296 struct { 05297 vuint8_t IBC:8; 05298 } B; 05299 } IBFD; /* Module Bus Frequency Register */ 05300 05301 union { 05302 vuint8_t R; 05303 struct { 05304 vuint8_t MDIS:1; 05305 vuint8_t IBIE:1; 05306 vuint8_t MS:1; 05307 vuint8_t TX:1; 05308 vuint8_t NOACK:1; 05309 vuint8_t RSTA:1; 05310 vuint8_t DMAEN:1; 05311 vuint8_t IBDOZE:1; 05312 } B; 05313 } IBCR; /* Module Bus Control Register */ 05314 05315 union { 05316 vuint8_t R; 05317 struct { 05318 vuint8_t TCF:1; 05319 vuint8_t IAAS:1; 05320 vuint8_t IBB:1; 05321 vuint8_t IBAL:1; 05322 vuint8_t:1; 05323 vuint8_t SRW:1; 05324 vuint8_t IBIF:1; 05325 vuint8_t RXAK:1; 05326 } B; 05327 } IBSR; /* Module Status Register */ 05328 05329 union { 05330 vuint8_t R; 05331 struct { 05332 vuint8_t DATA:8; 05333 } B; 05334 } IBDR; /* Module Data Register */ 05335 05336 union { 05337 vuint8_t R; 05338 struct { 05339 vuint8_t BIIE:1; 05340 vuint8_t:7; 05341 } B; 05342 } IBIC; /* Module Interrupt Configuration Register */ 05343 05344 }; /* end of I2C_tag */ 05345 /****************************************************************************/ 05346 /* MODULE : MPU */ 05347 /****************************************************************************/ 05348 struct MPU_tag { 05349 union { 05350 vuint32_t R; 05351 struct { 05352 vuint32_t SPERR:8; 05353 vuint32_t:4; 05354 vuint32_t HRL:4; 05355 vuint32_t NSP:4; 05356 vuint32_t NGRD:4; 05357 vuint32_t:7; 05358 vuint32_t VLD:1; 05359 } B; 05360 } CESR; /* Module Control/Error Status Register */ 05361 05362 uint32_t mpu_reserved1[3]; /* (0x010 - 0x004)/4 = 0x03 */ 05363 05364 union { 05365 vuint32_t R; 05366 struct { 05367 vuint32_t EADDR:32; 05368 } B; 05369 } EAR0; 05370 05371 union { 05372 vuint32_t R; 05373 struct { 05374 vuint32_t EACD:16; 05375 vuint32_t EPID:8; 05376 vuint32_t EMN:4; 05377 vuint32_t EATTR:3; 05378 vuint32_t ERW:1; 05379 } B; 05380 } EDR0; 05381 05382 union { 05383 vuint32_t R; 05384 struct { 05385 vuint32_t EADDR:32; 05386 } B; 05387 } EAR1; 05388 05389 union { 05390 vuint32_t R; 05391 struct { 05392 vuint32_t EACD:16; 05393 vuint32_t EPID:8; 05394 vuint32_t EMN:4; 05395 vuint32_t EATTR:3; 05396 vuint32_t ERW:1; 05397 } B; 05398 } EDR1; 05399 05400 union { 05401 vuint32_t R; 05402 struct { 05403 vuint32_t EADDR:32; 05404 } B; 05405 } EAR2; 05406 05407 union { 05408 vuint32_t R; 05409 struct { 05410 vuint32_t EACD:16; 05411 vuint32_t EPID:8; 05412 vuint32_t EMN:4; 05413 vuint32_t EATTR:3; 05414 vuint32_t ERW:1; 05415 } B; 05416 } EDR2; 05417 05418 union { 05419 vuint32_t R; 05420 struct { 05421 vuint32_t EADDR:32; 05422 } B; 05423 } EAR3; 05424 05425 union { 05426 vuint32_t R; 05427 struct { 05428 vuint32_t EACD:16; 05429 vuint32_t EPID:8; 05430 vuint32_t EMN:4; 05431 vuint32_t EATTR:3; 05432 vuint32_t ERW:1; 05433 } B; 05434 } EDR3; 05435 05436 uint32_t mpu_reserved2[244]; /* (0x0400 - 0x0030)/4 = 0x0F4 */ 05437 05438 struct { 05439 union { 05440 vuint32_t R; 05441 struct { 05442 vuint32_t SRTADDR:27; 05443 vuint32_t:5; 05444 } B; 05445 } WORD0; /* Region Descriptor n Word 0 */ 05446 05447 union { 05448 vuint32_t R; 05449 struct { 05450 vuint32_t ENDADDR:27; 05451 vuint32_t:5; 05452 } B; 05453 } WORD1; /* Region Descriptor n Word 1 */ 05454 05455 union { 05456 vuint32_t R; 05457 struct { 05458 vuint32_t M7RE:1; 05459 vuint32_t M7WE:1; 05460 vuint32_t M6RE:1; 05461 vuint32_t M6WE:1; 05462 vuint32_t M5RE:1; 05463 vuint32_t M5WE:1; 05464 vuint32_t M4RE:1; 05465 vuint32_t M4WE:1; 05466 vuint32_t M3PE:1; 05467 vuint32_t M3SM:2; 05468 vuint32_t M3UM:3; 05469 vuint32_t M2PE:1; 05470 vuint32_t M2SM:2; 05471 vuint32_t M2UM:3; 05472 vuint32_t M1PE:1; 05473 vuint32_t M1SM:2; 05474 vuint32_t M1UM:3; 05475 vuint32_t M0PE:1; 05476 vuint32_t M0SM:2; 05477 vuint32_t M0UM:3; 05478 } B; 05479 } WORD2; /* Region Descriptor n Word 2 */ 05480 05481 union { 05482 vuint32_t R; 05483 struct { 05484 vuint32_t PID:8; 05485 vuint32_t PIDMASK:8; 05486 vuint32_t:15; 05487 vuint32_t VLD:1; 05488 } B; 05489 } WORD3; /* Region Descriptor n Word 3 */ 05490 05491 } RGD[16]; 05492 05493 uint32_t mpu_reserved3[192]; /* (0x0800 - 0x0500)/4 = 0x0C0 */ 05494 05495 union { 05496 vuint32_t R; 05497 struct { 05498 vuint32_t M7RE:1; 05499 vuint32_t M7WE:1; 05500 vuint32_t M6RE:1; 05501 vuint32_t M6WE:1; 05502 vuint32_t M5RE:1; 05503 vuint32_t M5WE:1; 05504 vuint32_t M4RE:1; 05505 vuint32_t M4WE:1; 05506 vuint32_t M3PE:1; 05507 vuint32_t M3SM:2; 05508 vuint32_t M3UM:3; 05509 vuint32_t M2PE:1; 05510 vuint32_t M2SM:2; 05511 vuint32_t M2UM:3; 05512 vuint32_t M1PE:1; 05513 vuint32_t M1SM:2; 05514 vuint32_t M1UM:3; 05515 vuint32_t M0PE:1; 05516 vuint32_t M0SM:2; 05517 vuint32_t M0UM:3; 05518 } B; 05519 } RGDAAC[16]; /* Region Descriptor Alternate Access Control n */ 05520 05521 }; /* end of MPU_tag */ 05522 /****************************************************************************/ 05523 /* MODULE : eDMA */ 05524 /****************************************************************************/ 05525 05526 /*for "standard" format TCD (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0) */ 05527 struct EDMA_TCD_STD_tag { 05528 05529 vuint32_t SADDR; /* source address */ 05530 05531 vuint16_t SMOD:5; /* source address modulo */ 05532 vuint16_t SSIZE:3; /* source transfer size */ 05533 vuint16_t DMOD:5; /* destination address modulo */ 05534 vuint16_t DSIZE:3; /* destination transfer size */ 05535 vint16_t SOFF; /* signed source address offset */ 05536 05537 vuint32_t NBYTES; /* inner (“minor”) byte count */ 05538 05539 vint32_t SLAST; /* last destination address adjustment, or 05540 scatter/gather address (if e_sg = 1) */ 05541 05542 vuint32_t DADDR; /* destination address */ 05543 05544 vuint16_t CITERE_LINK:1; 05545 vuint16_t CITER:15; 05546 05547 vint16_t DOFF; /* signed destination address offset */ 05548 05549 vint32_t DLAST_SGA; 05550 05551 vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */ 05552 vuint16_t BITER:15; 05553 05554 vuint16_t BWC:2; /* bandwidth control */ 05555 vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */ 05556 vuint16_t DONE:1; /* channel done */ 05557 vuint16_t ACTIVE:1; /* channel active */ 05558 vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */ 05559 vuint16_t E_SG:1; /* enable scatter/gather descriptor */ 05560 vuint16_t D_REQ:1; /* disable ipd_req when done */ 05561 vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */ 05562 vuint16_t INT_MAJ:1; /* interrupt on major loop completion */ 05563 vuint16_t START:1; /* explicit channel start */ 05564 05565 }; /* end of EDMA_TCD_STD_tag */ 05566 05567 /*for "channel link" format TCD (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1)*/ 05568 struct EDMA_TCD_CHLINK_tag { 05569 05570 vuint32_t SADDR; /* source address */ 05571 05572 vuint16_t SMOD:5; /* source address modulo */ 05573 vuint16_t SSIZE:3; /* source transfer size */ 05574 vuint16_t DMOD:5; /* destination address modulo */ 05575 vuint16_t DSIZE:3; /* destination transfer size */ 05576 vint16_t SOFF; /* signed source address offset */ 05577 05578 vuint32_t NBYTES; /* inner (“minor”) byte count */ 05579 05580 vint32_t SLAST; /* last destination address adjustment, or 05581 scatter/gather address (if e_sg = 1) */ 05582 05583 vuint32_t DADDR; /* destination address */ 05584 05585 vuint16_t CITERE_LINK:1; 05586 vuint16_t CITERLINKCH:6; 05587 vuint16_t CITER:9; 05588 05589 vint16_t DOFF; /* signed destination address offset */ 05590 05591 vint32_t DLAST_SGA; 05592 05593 vuint16_t BITERE_LINK:1; /* beginning (“major”) iteration count */ 05594 vuint16_t BITERLINKCH:6; 05595 vuint16_t BITER:9; 05596 05597 vuint16_t BWC:2; /* bandwidth control */ 05598 vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */ 05599 vuint16_t DONE:1; /* channel done */ 05600 vuint16_t ACTIVE:1; /* channel active */ 05601 vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */ 05602 vuint16_t E_SG:1; /* enable scatter/gather descriptor */ 05603 vuint16_t D_REQ:1; /* disable ipd_req when done */ 05604 vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */ 05605 vuint16_t INT_MAJ:1; /* interrupt on major loop completion */ 05606 vuint16_t START:1; /* explicit channel start */ 05607 05608 }; /* end of EDMA_TCD_CHLINK_tag */ 05609 05610 struct EDMA_tag { 05611 union { 05612 vuint32_t R; 05613 struct { 05614 vuint32_t:29; 05615 vuint32_t ERCA:1; 05616 vuint32_t EDBG:1; 05617 vuint32_t:1; 05618 } B; 05619 } CR; /* Control Register */ 05620 05621 union { 05622 vuint32_t R; 05623 struct { 05624 vuint32_t VLD:1; 05625 vuint32_t:15; 05626 vuint32_t GPE:1; 05627 vuint32_t CPE:1; 05628 vuint32_t ERRCHN:6; 05629 vuint32_t SAE:1; 05630 vuint32_t SOE:1; 05631 vuint32_t DAE:1; 05632 vuint32_t DOE:1; 05633 vuint32_t NCE:1; 05634 vuint32_t SGE:1; 05635 vuint32_t SBE:1; 05636 vuint32_t DBE:1; 05637 } B; 05638 } ESR; /* Error Status Register */ 05639 05640 int16_t EDMA_reserved1[3]; /* (0x0E - 0x08)/2 = 0x03 */ 05641 05642 union { 05643 vuint16_t R; 05644 struct { 05645 vuint16_t ERQ15:1; 05646 vuint16_t ERQ14:1; 05647 vuint16_t ERQ13:1; 05648 vuint16_t ERQ12:1; 05649 vuint16_t ERQ11:1; 05650 vuint16_t ERQ10:1; 05651 vuint16_t ERQ09:1; 05652 vuint16_t ERQ08:1; 05653 vuint16_t ERQ07:1; 05654 vuint16_t ERQ06:1; 05655 vuint16_t ERQ05:1; 05656 vuint16_t ERQ04:1; 05657 vuint16_t ERQ03:1; 05658 vuint16_t ERQ02:1; 05659 vuint16_t ERQ01:1; 05660 vuint16_t ERQ00:1; 05661 } B; 05662 } ERQRL; /* DMA Enable Request Register Low */ 05663 05664 int16_t EDMA_reserved2[3]; /* (0x16 - 0x10)/2 = 0x03 */ 05665 05666 union { 05667 vuint16_t R; 05668 struct { 05669 vuint16_t EEI15:1; 05670 vuint16_t EEI14:1; 05671 vuint16_t EEI13:1; 05672 vuint16_t EEI12:1; 05673 vuint16_t EEI11:1; 05674 vuint16_t EEI10:1; 05675 vuint16_t EEI09:1; 05676 vuint16_t EEI08:1; 05677 vuint16_t EEI07:1; 05678 vuint16_t EEI06:1; 05679 vuint16_t EEI05:1; 05680 vuint16_t EEI04:1; 05681 vuint16_t EEI03:1; 05682 vuint16_t EEI02:1; 05683 vuint16_t EEI01:1; 05684 vuint16_t EEI00:1; 05685 } B; 05686 } EEIRL; /* DMA Enable Error Interrupt Register Low */ 05687 05688 union { 05689 vuint8_t R; 05690 struct { 05691 vuint8_t:1; 05692 vuint8_t SERQ:7; 05693 } B; 05694 } SERQR; /* DMA Set Enable Request Register */ 05695 05696 union { 05697 vuint8_t R; 05698 struct { 05699 vuint8_t:1; 05700 vuint8_t CERQ:7; 05701 } B; 05702 } CERQR; /* DMA Clear Enable Request Register */ 05703 05704 union { 05705 vuint8_t R; 05706 struct { 05707 vuint8_t:1; 05708 vuint8_t SEEI:7; 05709 } B; 05710 } SEEIR; /* DMA Set Enable Error Interrupt Register */ 05711 05712 union { 05713 vuint8_t R; 05714 struct { 05715 vuint8_t:1; 05716 vuint8_t CEEI:7; 05717 } B; 05718 } CEEIR; /* DMA Clear Enable Error Interrupt Register */ 05719 05720 union { 05721 vuint8_t R; 05722 struct { 05723 vuint8_t:1; 05724 vuint8_t CINT:7; 05725 } B; 05726 } CIRQR; /* DMA Clear Interrupt Request Register */ 05727 05728 union { 05729 vuint8_t R; 05730 struct { 05731 vuint8_t:1; 05732 vuint8_t CER:7; 05733 } B; 05734 } CERR; /* DMA Clear error Register */ 05735 05736 union { 05737 vuint8_t R; 05738 struct { 05739 vuint8_t:1; 05740 vuint8_t SSB:7; 05741 } B; 05742 } SSBR; /* Set Start Bit Register */ 05743 05744 union { 05745 vuint8_t R; 05746 struct { 05747 vuint8_t:1; 05748 vuint8_t CDSB:7; 05749 } B; 05750 } CDSBR; /* Clear Done Status Bit Register */ 05751 05752 int16_t EDMA_reserved3[3]; /* (0x26 - 0x20)/2 = 0x03 */ 05753 05754 union { 05755 vuint16_t R; 05756 struct { 05757 vuint16_t INT15:1; 05758 vuint16_t INT14:1; 05759 vuint16_t INT13:1; 05760 vuint16_t INT12:1; 05761 vuint16_t INT11:1; 05762 vuint16_t INT10:1; 05763 vuint16_t INT09:1; 05764 vuint16_t INT08:1; 05765 vuint16_t INT07:1; 05766 vuint16_t INT06:1; 05767 vuint16_t INT05:1; 05768 vuint16_t INT04:1; 05769 vuint16_t INT03:1; 05770 vuint16_t INT02:1; 05771 vuint16_t INT01:1; 05772 vuint16_t INT00:1; 05773 } B; 05774 } IRQRL; /* DMA Interrupt Request Low */ 05775 05776 int16_t EDMA_reserved4[3]; /* (0x2E - 0x28)/2 = 0x03 */ 05777 05778 union { 05779 vuint16_t R; 05780 struct { 05781 vuint16_t ERR15:1; 05782 vuint16_t ERR14:1; 05783 vuint16_t ERR13:1; 05784 vuint16_t ERR12:1; 05785 vuint16_t ERR11:1; 05786 vuint16_t ERR10:1; 05787 vuint16_t ERR09:1; 05788 vuint16_t ERR08:1; 05789 vuint16_t ERR07:1; 05790 vuint16_t ERR06:1; 05791 vuint16_t ERR05:1; 05792 vuint16_t ERR04:1; 05793 vuint16_t ERR03:1; 05794 vuint16_t ERR02:1; 05795 vuint16_t ERR01:1; 05796 vuint16_t ERR00:1; 05797 } B; 05798 } ERL; /* DMA Error Low */ 05799 05800 int16_t EDMA_reserved5[3]; /* (0x36 - 0x30)/2 = 0x03 */ 05801 05802 union { 05803 vuint16_t R; 05804 struct { 05805 vuint16_t HRS15:1; 05806 vuint16_t HRS14:1; 05807 vuint16_t HRS13:1; 05808 vuint16_t HRS12:1; 05809 vuint16_t HRS11:1; 05810 vuint16_t HRS10:1; 05811 vuint16_t HRS09:1; 05812 vuint16_t HRS08:1; 05813 vuint16_t HRS07:1; 05814 vuint16_t HRS06:1; 05815 vuint16_t HRS05:1; 05816 vuint16_t HRS04:1; 05817 vuint16_t HRS03:1; 05818 vuint16_t HRS02:1; 05819 vuint16_t HRS01:1; 05820 vuint16_t HRS00:1; 05821 } B; 05822 } HRSL; /* DMA Hardware Request Status Low */ 05823 05824 uint32_t edma_reserved1[50]; /* (0x100 - 0x038)/4 = 0x32 */ 05825 05826 union { 05827 vuint8_t R; 05828 struct { 05829 vuint8_t ECP:1; 05830 vuint8_t DPA:1; 05831 vuint8_t GRPPRI:2; 05832 vuint8_t CHPRI:4; 05833 } B; 05834 } CPR[16]; /* Channel n Priority */ 05835 05836 uint32_t edma_reserved2[956]; /* (0x1000 - 0x0110)/4 = 0x3BC */ 05837 05838 struct EDMA_TCD_STD_tag TCD[16]; 05839 /* struct EDMA_TCD_CHLINK_tag TCD[16]; */ 05840 05841 }; /* end of EDMA_tag */ 05842 /****************************************************************************/ 05843 /* MODULE : INTC */ 05844 /****************************************************************************/ 05845 struct INTC_tag { 05846 union { 05847 vuint32_t R; 05848 struct { 05849 vuint32_t:26; 05850 vuint32_t VTES:1; 05851 vuint32_t:4; 05852 vuint32_t HVEN:1; 05853 } B; 05854 } MCR; /* Module Configuration Register */ 05855 05856 int32_t INTC_reserved1; /* (0x008 - 0x004)/4 = 0x01 */ 05857 05858 union { 05859 vuint32_t R; 05860 struct { 05861 vuint32_t:28; 05862 vuint32_t PRI:4; 05863 } B; 05864 } CPR; /* Current Priority Register */ 05865 05866 int32_t INTC_reserved2; /* (0x010 - 0x00C)/4 = 0x01 */ 05867 05868 union { 05869 vuint32_t R; 05870 struct { 05871 vuint32_t VTBA:21; 05872 vuint32_t INTVEC:9; 05873 vuint32_t:2; 05874 } B; 05875 } IACKR; /* Interrupt Acknowledge Register */ 05876 05877 int32_t INTC_reserved3; /* (0x018 - 0x014)/4 = 0x01 */ 05878 05879 union { 05880 vuint32_t R; 05881 struct { 05882 vuint32_t:32; 05883 } B; 05884 } EOIR; /* End of Interrupt Register */ 05885 05886 int32_t INTC_reserved4; /* (0x020 - 0x01C)/4 = 0x01 */ 05887 05888 union { 05889 vuint8_t R; 05890 struct { 05891 vuint8_t:6; 05892 vuint8_t SET:1; 05893 vuint8_t CLR:1; 05894 } B; 05895 } SSCIR[8]; /* Software Set/Clear Interruput Register */ 05896 05897 uint32_t intc_reserved5[6]; /* (0x040 - 0x028)/4 = 0x06 */ 05898 05899 union { 05900 vuint8_t R; 05901 struct { 05902 vuint8_t:4; 05903 vuint8_t PRI:4; 05904 } B; 05905 } PSR[512]; /* Software Set/Clear Interrupt Register */ 05906 05907 }; /* end of INTC_tag */ 05908 /****************************************************************************/ 05909 /* MODULE : DSPI */ 05910 /****************************************************************************/ 05911 struct DSPI_tag { 05912 union { 05913 vuint32_t R; 05914 struct { 05915 vuint32_t MSTR:1; 05916 vuint32_t CONT_SCKE:1; 05917 vuint32_t DCONF:2; 05918 vuint32_t FRZ:1; 05919 vuint32_t MTFE:1; 05920 vuint32_t PCSSE:1; 05921 vuint32_t ROOE:1; 05922 vuint32_t PCSIS7:1; 05923 vuint32_t PCSIS6:1; 05924 vuint32_t PCSIS5:1; 05925 vuint32_t PCSIS4:1; 05926 vuint32_t PCSIS3:1; 05927 vuint32_t PCSIS2:1; 05928 vuint32_t PCSIS1:1; 05929 vuint32_t PCSIS0:1; 05930 vuint32_t DOZE:1; 05931 vuint32_t MDIS:1; 05932 vuint32_t DIS_TXF:1; 05933 vuint32_t DIS_RXF:1; 05934 vuint32_t CLR_TXF:1; 05935 vuint32_t CLR_RXF:1; 05936 vuint32_t SMPL_PT:2; 05937 vuint32_t:7; 05938 vuint32_t HALT:1; 05939 } B; 05940 } MCR; /* Module Configuration Register */ 05941 05942 uint32_t dspi_reserved1; 05943 05944 union { 05945 vuint32_t R; 05946 struct { 05947 vuint32_t TCNT:16; 05948 vuint32_t:16; 05949 } B; 05950 } TCR; 05951 05952 union { 05953 vuint32_t R; 05954 struct { 05955 vuint32_t DBR:1; 05956 vuint32_t FMSZ:4; 05957 vuint32_t CPOL:1; 05958 vuint32_t CPHA:1; 05959 vuint32_t LSBFE:1; 05960 vuint32_t PCSSCK:2; 05961 vuint32_t PASC:2; 05962 vuint32_t PDT:2; 05963 vuint32_t PBR:2; 05964 vuint32_t CSSCK:4; 05965 vuint32_t ASC:4; 05966 vuint32_t DT:4; 05967 vuint32_t BR:4; 05968 } B; 05969 } CTAR[8]; /* Clock and Transfer Attributes Registers */ 05970 05971 union { 05972 vuint32_t R; 05973 struct { 05974 vuint32_t TCF:1; 05975 vuint32_t TXRXS:1; 05976 vuint32_t:1; 05977 vuint32_t EOQF:1; 05978 vuint32_t TFUF:1; 05979 vuint32_t:1; 05980 vuint32_t TFFF:1; 05981 vuint32_t:5; 05982 vuint32_t RFOF:1; 05983 vuint32_t:1; 05984 vuint32_t RFDF:1; 05985 vuint32_t:1; 05986 vuint32_t TXCTR:4; 05987 vuint32_t TXNXTPTR:4; 05988 vuint32_t RXCTR:4; 05989 vuint32_t POPNXTPTR:4; 05990 } B; 05991 } SR; /* Status Register */ 05992 05993 union { 05994 vuint32_t R; 05995 struct { 05996 vuint32_t TCFRE:1; 05997 vuint32_t:2; 05998 vuint32_t EOQFRE:1; 05999 vuint32_t TFUFRE:1; 06000 vuint32_t:1; 06001 vuint32_t TFFFRE:1; 06002 vuint32_t TFFFDIRS:1; 06003 vuint32_t:4; 06004 vuint32_t RFOFRE:1; 06005 vuint32_t:1; 06006 vuint32_t RFDFRE:1; 06007 vuint32_t RFDFDIRS:1; 06008 vuint32_t:16; 06009 } B; 06010 } RSER; /* DMA/Interrupt Request Select and Enable Register */ 06011 06012 union { 06013 vuint32_t R; 06014 struct { 06015 vuint32_t CONT:1; 06016 vuint32_t CTAS:3; 06017 vuint32_t EOQ:1; 06018 vuint32_t CTCNT:1; 06019 vuint32_t:2; 06020 vuint32_t PCS7:1; 06021 vuint32_t PCS6:1; 06022 vuint32_t PCS5:1; 06023 vuint32_t PCS4:1; 06024 vuint32_t PCS3:1; 06025 vuint32_t PCS2:1; 06026 vuint32_t PCS1:1; 06027 vuint32_t PCS0:1; 06028 vuint32_t TXDATA:16; 06029 } B; 06030 } PUSHR; /* PUSH TX FIFO Register */ 06031 06032 union { 06033 vuint32_t R; 06034 struct { 06035 vuint32_t:16; 06036 vuint32_t RXDATA:16; 06037 } B; 06038 } POPR; /* POP RX FIFO Register */ 06039 06040 union { 06041 vuint32_t R; 06042 struct { 06043 vuint32_t TXCMD:16; 06044 vuint32_t TXDATA:16; 06045 } B; 06046 } TXFR[4]; /* Transmit FIFO Registers */ 06047 06048 vuint32_t DSPI_reserved_txf[12]; 06049 06050 union { 06051 vuint32_t R; 06052 struct { 06053 vuint32_t:16; 06054 vuint32_t RXDATA:16; 06055 } B; 06056 } RXFR[4]; /* Transmit FIFO Registers */ 06057 06058 vuint32_t DSPI_reserved_rxf[12]; 06059 06060 union { 06061 vuint32_t R; 06062 struct { 06063 vuint32_t MTOE:1; 06064 vuint32_t:1; 06065 vuint32_t MTOCNT:6; 06066 vuint32_t:4; 06067 vuint32_t TXSS:1; 06068 vuint32_t TPOL:1; 06069 vuint32_t TRRE:1; 06070 vuint32_t CID:1; 06071 vuint32_t DCONT:1; 06072 vuint32_t DSICTAS:3; 06073 vuint32_t:6; 06074 vuint32_t DPCS5:1; 06075 vuint32_t DPCS4:1; 06076 vuint32_t DPCS3:1; 06077 vuint32_t DPCS2:1; 06078 vuint32_t DPCS1:1; 06079 vuint32_t DPCS0:1; 06080 } B; 06081 } DSICR; /* DSI Configuration Register */ 06082 06083 union { 06084 vuint32_t R; 06085 struct { 06086 vuint32_t:16; 06087 vuint32_t SER_DATA:16; 06088 } B; 06089 } SDR; /* DSI Serialization Data Register */ 06090 06091 union { 06092 vuint32_t R; 06093 struct { 06094 vuint32_t:16; 06095 vuint32_t ASER_DATA:16; 06096 } B; 06097 } ASDR; /* DSI Alternate Serialization Data Register */ 06098 06099 union { 06100 vuint32_t R; 06101 struct { 06102 vuint32_t:16; 06103 vuint32_t COMP_DATA:16; 06104 } B; 06105 } COMPR; /* DSI Transmit Comparison Register */ 06106 06107 union { 06108 vuint32_t R; 06109 struct { 06110 vuint32_t:16; 06111 vuint32_t DESER_DATA:16; 06112 } B; 06113 } DDR; /* DSI deserialization Data Register */ 06114 06115 }; /* end of DSPI_tag */ 06116 /****************************************************************************/ 06117 /* MODULE : FlexCAN */ 06118 /****************************************************************************/ 06119 struct FLEXCAN_BUF_t { 06120 union { 06121 vuint32_t R; 06122 struct { 06123 vuint32_t:4; 06124 vuint32_t CODE:4; 06125 vuint32_t:1; 06126 vuint32_t SRR:1; 06127 vuint32_t IDE:1; 06128 vuint32_t RTR:1; 06129 vuint32_t LENGTH:4; 06130 vuint32_t TIMESTAMP:16; 06131 } B; 06132 } CS; 06133 06134 union { 06135 vuint32_t R; 06136 struct { 06137 vuint32_t PRIO:3; 06138 vuint32_t STD_ID:11; 06139 vuint32_t EXT_ID:18; 06140 } B; 06141 } ID; 06142 06143 union { 06144 /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) */ 06145 /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) */ 06146 vuint32_t W[2]; /* Data buffer in words (32 bits) */ 06147 /*vuint32_t R[2]; *//* Data buffer in words (32 bits) */ 06148 } DATA; 06149 06150 }; /* end of FLEXCAN_BUF_t */ 06151 06152 struct FLEXCAN_RXFIFO_t { 06153 union { 06154 vuint32_t R; 06155 struct { 06156 vuint32_t:9; 06157 vuint32_t SRR:1; 06158 vuint32_t IDE:1; 06159 vuint32_t RTR:1; 06160 vuint32_t LENGTH:4; 06161 vuint32_t TIMESTAMP:16; 06162 } B; 06163 } CS; 06164 06165 union { 06166 vuint32_t R; 06167 struct { 06168 vuint32_t:3; 06169 vuint32_t STD_ID:11; 06170 vuint32_t EXT_ID:18; 06171 } B; 06172 } ID; 06173 06174 union { 06175 /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) */ 06176 /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) */ 06177 vuint32_t W[2]; /* Data buffer in words (32 bits) */ 06178 /*vuint32_t R[2]; *//* Data buffer in words (32 bits) */ 06179 } DATA; 06180 06181 uint32_t FLEXCAN_RXFIFO_reserved[20]; /* {0x00E0-0x0090}/0x4 = 0x14 */ 06182 06183 union { 06184 vuint32_t R; 06185 } IDTABLE[8]; 06186 06187 }; /* end of FLEXCAN_RXFIFO_t */ 06188 06189 struct FLEXCAN_tag { 06190 union { 06191 vuint32_t R; 06192 struct { 06193 vuint32_t MDIS:1; 06194 vuint32_t FRZ:1; 06195 vuint32_t FEN:1; 06196 vuint32_t HALT:1; 06197 vuint32_t NOTRDY:1; 06198 vuint32_t WAKMSK:1; 06199 vuint32_t SOFTRST:1; 06200 vuint32_t FRZACK:1; 06201 vuint32_t SUPV:1; 06202 vuint32_t SLFWAK:1; 06203 vuint32_t WRNEN:1; 06204 vuint32_t LPMACK:1; 06205 vuint32_t WAKSRC:1; 06206 vuint32_t DOZE:1; 06207 vuint32_t SRXDIS:1; 06208 vuint32_t BCC:1; 06209 vuint32_t:2; 06210 vuint32_t LPRIO_EN:1; 06211 vuint32_t AEN:1; 06212 vuint32_t:2; 06213 vuint32_t IDAM:2; 06214 vuint32_t:2; 06215 vuint32_t MAXMB:6; 06216 } B; 06217 } MCR; /* Module Configuration Register */ 06218 06219 union { 06220 vuint32_t R; 06221 struct { 06222 vuint32_t PRESDIV:8; 06223 vuint32_t RJW:2; 06224 vuint32_t PSEG1:3; 06225 vuint32_t PSEG2:3; 06226 vuint32_t BOFFMSK:1; 06227 vuint32_t ERRMSK:1; 06228 vuint32_t CLKSRC:1; 06229 vuint32_t LPB:1; 06230 vuint32_t TWRNMSK:1; 06231 vuint32_t RWRNMSK:1; 06232 vuint32_t:2; 06233 vuint32_t SMP:1; 06234 vuint32_t BOFFREC:1; 06235 vuint32_t TSYN:1; 06236 vuint32_t LBUF:1; 06237 vuint32_t LOM:1; 06238 vuint32_t PROPSEG:3; 06239 } B; 06240 } CR; /* Control Register */ 06241 06242 union { 06243 vuint32_t R; 06244 } TIMER; /* Free Running Timer */ 06245 06246 uint32_t FLEXCAN_reserved1; 06247 06248 union { 06249 vuint32_t R; 06250 struct { 06251 vuint32_t MI:32; 06252 } B; 06253 } RXGMASK; /* RX Global Mask */ 06254 06255 union { 06256 vuint32_t R; 06257 struct { 06258 vuint32_t MI:32; 06259 } B; 06260 } RX14MASK; /* RX 14 Mask */ 06261 06262 union { 06263 vuint32_t R; 06264 struct { 06265 vuint32_t MI:32; 06266 } B; 06267 } RX15MASK; /* RX 15 Mask */ 06268 06269 union { 06270 vuint32_t R; 06271 struct { 06272 vuint32_t:16; 06273 vuint32_t RXECNT:8; 06274 vuint32_t TXECNT:8; 06275 } B; 06276 } ECR; /* Error Counter Register */ 06277 06278 union { 06279 vuint32_t R; 06280 struct { 06281 vuint32_t:14; 06282 vuint32_t TWRNINT:1; 06283 vuint32_t RWRNINT:1; 06284 vuint32_t BIT1ERR:1; 06285 vuint32_t BIT0ERR:1; 06286 vuint32_t ACKERR:1; 06287 vuint32_t CRCERR:1; 06288 vuint32_t FRMERR:1; 06289 vuint32_t STFERR:1; 06290 vuint32_t TXWRN:1; 06291 vuint32_t RXWRN:1; 06292 vuint32_t IDLE:1; 06293 vuint32_t TXRX:1; 06294 vuint32_t FLTCONF:2; 06295 vuint32_t:1; 06296 vuint32_t BOFFINT:1; 06297 vuint32_t ERRINT:1; 06298 vuint32_t WAKINT:1; 06299 } B; 06300 } ESR; /* Error and Status Register */ 06301 06302 union { 06303 vuint32_t R; 06304 struct { 06305 vuint32_t BUF63M:1; 06306 vuint32_t BUF62M:1; 06307 vuint32_t BUF61M:1; 06308 vuint32_t BUF60M:1; 06309 vuint32_t BUF59M:1; 06310 vuint32_t BUF58M:1; 06311 vuint32_t BUF57M:1; 06312 vuint32_t BUF56M:1; 06313 vuint32_t BUF55M:1; 06314 vuint32_t BUF54M:1; 06315 vuint32_t BUF53M:1; 06316 vuint32_t BUF52M:1; 06317 vuint32_t BUF51M:1; 06318 vuint32_t BUF50M:1; 06319 vuint32_t BUF49M:1; 06320 vuint32_t BUF48M:1; 06321 vuint32_t BUF47M:1; 06322 vuint32_t BUF46M:1; 06323 vuint32_t BUF45M:1; 06324 vuint32_t BUF44M:1; 06325 vuint32_t BUF43M:1; 06326 vuint32_t BUF42M:1; 06327 vuint32_t BUF41M:1; 06328 vuint32_t BUF40M:1; 06329 vuint32_t BUF39M:1; 06330 vuint32_t BUF38M:1; 06331 vuint32_t BUF37M:1; 06332 vuint32_t BUF36M:1; 06333 vuint32_t BUF35M:1; 06334 vuint32_t BUF34M:1; 06335 vuint32_t BUF33M:1; 06336 vuint32_t BUF32M:1; 06337 } B; 06338 } IMRH; /* Interruput Masks Register */ 06339 06340 union { 06341 vuint32_t R; 06342 struct { 06343 vuint32_t BUF31M:1; 06344 vuint32_t BUF30M:1; 06345 vuint32_t BUF29M:1; 06346 vuint32_t BUF28M:1; 06347 vuint32_t BUF27M:1; 06348 vuint32_t BUF26M:1; 06349 vuint32_t BUF25M:1; 06350 vuint32_t BUF24M:1; 06351 vuint32_t BUF23M:1; 06352 vuint32_t BUF22M:1; 06353 vuint32_t BUF21M:1; 06354 vuint32_t BUF20M:1; 06355 vuint32_t BUF19M:1; 06356 vuint32_t BUF18M:1; 06357 vuint32_t BUF17M:1; 06358 vuint32_t BUF16M:1; 06359 vuint32_t BUF15M:1; 06360 vuint32_t BUF14M:1; 06361 vuint32_t BUF13M:1; 06362 vuint32_t BUF12M:1; 06363 vuint32_t BUF11M:1; 06364 vuint32_t BUF10M:1; 06365 vuint32_t BUF09M:1; 06366 vuint32_t BUF08M:1; 06367 vuint32_t BUF07M:1; 06368 vuint32_t BUF06M:1; 06369 vuint32_t BUF05M:1; 06370 vuint32_t BUF04M:1; 06371 vuint32_t BUF03M:1; 06372 vuint32_t BUF02M:1; 06373 vuint32_t BUF01M:1; 06374 vuint32_t BUF00M:1; 06375 } B; 06376 } IMRL; /* Interruput Masks Register */ 06377 06378 union { 06379 vuint32_t R; 06380 struct { 06381 vuint32_t BUF63I:1; 06382 vuint32_t BUF62I:1; 06383 vuint32_t BUF61I:1; 06384 vuint32_t BUF60I:1; 06385 vuint32_t BUF59I:1; 06386 vuint32_t BUF58I:1; 06387 vuint32_t BUF57I:1; 06388 vuint32_t BUF56I:1; 06389 vuint32_t BUF55I:1; 06390 vuint32_t BUF54I:1; 06391 vuint32_t BUF53I:1; 06392 vuint32_t BUF52I:1; 06393 vuint32_t BUF51I:1; 06394 vuint32_t BUF50I:1; 06395 vuint32_t BUF49I:1; 06396 vuint32_t BUF48I:1; 06397 vuint32_t BUF47I:1; 06398 vuint32_t BUF46I:1; 06399 vuint32_t BUF45I:1; 06400 vuint32_t BUF44I:1; 06401 vuint32_t BUF43I:1; 06402 vuint32_t BUF42I:1; 06403 vuint32_t BUF41I:1; 06404 vuint32_t BUF40I:1; 06405 vuint32_t BUF39I:1; 06406 vuint32_t BUF38I:1; 06407 vuint32_t BUF37I:1; 06408 vuint32_t BUF36I:1; 06409 vuint32_t BUF35I:1; 06410 vuint32_t BUF34I:1; 06411 vuint32_t BUF33I:1; 06412 vuint32_t BUF32I:1; 06413 } B; 06414 } IFRH; /* Interruput Flag Register */ 06415 06416 union { 06417 vuint32_t R; 06418 struct { 06419 vuint32_t BUF31I:1; 06420 vuint32_t BUF30I:1; 06421 vuint32_t BUF29I:1; 06422 vuint32_t BUF28I:1; 06423 vuint32_t BUF27I:1; 06424 vuint32_t BUF26I:1; 06425 vuint32_t BUF25I:1; 06426 vuint32_t BUF24I:1; 06427 vuint32_t BUF23I:1; 06428 vuint32_t BUF22I:1; 06429 vuint32_t BUF21I:1; 06430 vuint32_t BUF20I:1; 06431 vuint32_t BUF19I:1; 06432 vuint32_t BUF18I:1; 06433 vuint32_t BUF17I:1; 06434 vuint32_t BUF16I:1; 06435 vuint32_t BUF15I:1; 06436 vuint32_t BUF14I:1; 06437 vuint32_t BUF13I:1; 06438 vuint32_t BUF12I:1; 06439 vuint32_t BUF11I:1; 06440 vuint32_t BUF10I:1; 06441 vuint32_t BUF09I:1; 06442 vuint32_t BUF08I:1; 06443 vuint32_t BUF07I:1; 06444 vuint32_t BUF06I:1; 06445 vuint32_t BUF05I:1; 06446 vuint32_t BUF04I:1; 06447 vuint32_t BUF03I:1; 06448 vuint32_t BUF02I:1; 06449 vuint32_t BUF01I:1; 06450 vuint32_t BUF00I:1; 06451 } B; 06452 } IFRL; /* Interruput Flag Register */ 06453 06454 uint32_t FLEXCAN_reserved2[19]; /* {0x0080-0x0034}/0x4 = 0x13 */ 06455 06456 /****************************************************************************/ 06457 /* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */ 06458 /****************************************************************************/ 06459 /* Standard Buffer Structure */ 06460 struct FLEXCAN_BUF_t BUF[64]; 06461 06462 /* RX FIFO and Buffer Structure */ 06463 /*struct FLEXCAN_RXFIFO_t RXFIFO; */ 06464 /*struct FLEXCAN_BUF_t BUF[56]; */ 06465 /****************************************************************************/ 06466 06467 uint32_t FLEXCAN_reserved3[256]; /* {0x0880-0x0480}/0x4 = 0x100 */ 06468 06469 union { 06470 vuint32_t R; 06471 struct { 06472 vuint32_t MI:32; 06473 } B; 06474 } RXIMR[64]; /* RX Individual Mask Registers */ 06475 06476 }; /* end of FLEXCAN_tag */ 06477 /****************************************************************************/ 06478 /* MODULE : DMAMUX */ 06479 /****************************************************************************/ 06480 struct DMAMUX_tag { 06481 union { 06482 vuint8_t R; 06483 struct { 06484 vuint8_t ENBL:1; 06485 vuint8_t TRIG:1; 06486 vuint8_t SOURCE:6; 06487 } B; 06488 } CHCONFIG[16]; /* DMA Channel Configuration Register */ 06489 06490 }; /* end of DMAMUX_tag */ 06491 /****************************************************************************/ 06492 /* MODULE : FlexRay */ 06493 /****************************************************************************/ 06494 06495 typedef union uMVR { 06496 vuint16_t R; 06497 struct { 06498 vuint16_t CHIVER:8; /* CHI Version Number */ 06499 vuint16_t PEVER:8; /* PE Version Number */ 06500 } B; 06501 } MVR_t; 06502 06503 typedef union uMCR { 06504 vuint16_t R; 06505 struct { 06506 vuint16_t MEN:1; /* module enable */ 06507 vuint16_t:1; 06508 vuint16_t SCMD:1; /* single channel mode */ 06509 vuint16_t CHB:1; /* channel B enable */ 06510 vuint16_t CHA:1; /* channel A enable */ 06511 vuint16_t SFFE:1; /* synchronization frame filter enable */ 06512 vuint16_t:5; 06513 vuint16_t CLKSEL:1; /* protocol engine clock source select */ 06514 vuint16_t PRESCALE:3; /* protocol engine clock prescaler */ 06515 vuint16_t:1; 06516 } B; 06517 } MCR_t; 06518 typedef union uSTBSCR { 06519 vuint16_t R; 06520 struct { 06521 vuint16_t WMD:1; /* write mode */ 06522 vuint16_t STBSSEL:7; /* strobe signal select */ 06523 vuint16_t:3; 06524 vuint16_t ENB:1; /* strobe signal enable */ 06525 vuint16_t:2; 06526 vuint16_t STBPSEL:2; /* strobe port select */ 06527 } B; 06528 } STBSCR_t; 06529 typedef union uSTBPCR { 06530 vuint16_t R; 06531 struct { 06532 vuint16_t:12; 06533 vuint16_t STB3EN:1; /* strobe port enable */ 06534 vuint16_t STB2EN:1; /* strobe port enable */ 06535 vuint16_t STB1EN:1; /* strobe port enable */ 06536 vuint16_t STB0EN:1; /* strobe port enable */ 06537 } B; 06538 } STBPCR_t; 06539 06540 typedef union uMBDSR { 06541 vuint16_t R; 06542 struct { 06543 vuint16_t:1; 06544 vuint16_t MBSEG2DS:7; /* message buffer segment 2 data size */ 06545 vuint16_t:1; 06546 vuint16_t MBSEG1DS:7; /* message buffer segment 1 data size */ 06547 } B; 06548 } MBDSR_t; 06549 06550 typedef union uMBSSUTR { 06551 vuint16_t R; 06552 struct { 06553 06554 vuint16_t:2; 06555 vuint16_t LAST_MB_SEG1:6; /* last message buffer control register for message buffer segment 1 */ 06556 vuint16_t:2; 06557 vuint16_t LAST_MB_UTIL:6; /* last message buffer utilized */ 06558 } B; 06559 } MBSSUTR_t; 06560 06561 typedef union uPOCR { 06562 vuint16_t R; 06563 vuint8_t byte[2]; 06564 struct { 06565 vuint16_t WME:1; /* write mode external correction command */ 06566 vuint16_t:3; 06567 vuint16_t EOC_AP:2; /* external offset correction application */ 06568 vuint16_t ERC_AP:2; /* external rate correction application */ 06569 vuint16_t BSY:1; /* command write busy / write mode command */ 06570 vuint16_t:3; 06571 vuint16_t POCCMD:4; /* protocol command */ 06572 } B; 06573 } POCR_t; 06574 /* protocol commands */ 06575 typedef union uGIFER { 06576 vuint16_t R; 06577 struct { 06578 vuint16_t MIF:1; /* module interrupt flag */ 06579 vuint16_t PRIF:1; /* protocol interrupt flag */ 06580 vuint16_t CHIF:1; /* CHI interrupt flag */ 06581 vuint16_t WKUPIF:1; /* wakeup interrupt flag */ 06582 vuint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */ 06583 vuint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */ 06584 vuint16_t RBIF:1; /* receive message buffer interrupt flag */ 06585 vuint16_t TBIF:1; /* transmit buffer interrupt flag */ 06586 vuint16_t MIE:1; /* module interrupt enable */ 06587 vuint16_t PRIE:1; /* protocol interrupt enable */ 06588 vuint16_t CHIE:1; /* CHI interrupt enable */ 06589 vuint16_t WKUPIE:1; /* wakeup interrupt enable */ 06590 vuint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */ 06591 vuint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */ 06592 vuint16_t RBIE:1; /* receive message buffer interrupt enable */ 06593 vuint16_t TBIE:1; /* transmit buffer interrupt enable */ 06594 } B; 06595 } GIFER_t; 06596 typedef union uPIFR0 { 06597 vuint16_t R; 06598 struct { 06599 vuint16_t FATLIF:1; /* fatal protocol error interrupt flag */ 06600 vuint16_t INTLIF:1; /* internal protocol error interrupt flag */ 06601 vuint16_t ILCFIF:1; /* illegal protocol configuration flag */ 06602 vuint16_t CSAIF:1; /* cold start abort interrupt flag */ 06603 vuint16_t MRCIF:1; /* missing rate correctio interrupt flag */ 06604 vuint16_t MOCIF:1; /* missing offset correctio interrupt flag */ 06605 vuint16_t CCLIF:1; /* clock correction limit reached interrupt flag */ 06606 vuint16_t MXSIF:1; /* max sync frames detected interrupt flag */ 06607 vuint16_t MTXIF:1; /* media access test symbol received flag */ 06608 vuint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */ 06609 vuint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */ 06610 vuint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */ 06611 vuint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */ 06612 vuint16_t TI2IF:1; /* timer 2 expired interrupt flag */ 06613 vuint16_t TI1IF:1; /* timer 1 expired interrupt flag */ 06614 vuint16_t CYSIF:1; /* cycle start interrupt flag */ 06615 } B; 06616 } PIFR0_t; 06617 typedef union uPIFR1 { 06618 vuint16_t R; 06619 struct { 06620 vuint16_t EMCIF:1; /* error mode changed interrupt flag */ 06621 vuint16_t IPCIF:1; /* illegal protocol command interrupt flag */ 06622 vuint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */ 06623 vuint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */ 06624 vuint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */ 06625 vuint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */ 06626 vuint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */ 06627 vuint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */ 06628 vuint16_t:2; 06629 vuint16_t EVTIF:1; /* even cycle table written interrupt flag */ 06630 vuint16_t ODTIF:1; /* odd cycle table written interrupt flag */ 06631 vuint16_t:4; 06632 } B; 06633 } PIFR1_t; 06634 typedef union uPIER0 { 06635 vuint16_t R; 06636 struct { 06637 vuint16_t FATLIE:1; /* fatal protocol error interrupt enable */ 06638 vuint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */ 06639 vuint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */ 06640 vuint16_t CSAIE:1; /* cold start abort interrupt enable */ 06641 vuint16_t MRCIE:1; /* missing rate correctio interrupt enable */ 06642 vuint16_t MOCIE:1; /* missing offset correctio interrupt enable */ 06643 vuint16_t CCLIE:1; /* clock correction limit reached interrupt enable */ 06644 vuint16_t MXSIE:1; /* max sync frames detected interrupt enable */ 06645 vuint16_t MTXIE:1; /* media access test symbol received interrupt enable */ 06646 vuint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */ 06647 vuint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */ 06648 vuint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */ 06649 vuint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */ 06650 vuint16_t TI2IE:1; /* timer 2 expired interrupt enable */ 06651 vuint16_t TI1IE:1; /* timer 1 expired interrupt enable */ 06652 vuint16_t CYSIE:1; /* cycle start interrupt enable */ 06653 } B; 06654 } PIER0_t; 06655 typedef union uPIER1 { 06656 vuint16_t R; 06657 struct { 06658 vuint16_t EMCIE:1; /* error mode changed interrupt enable */ 06659 vuint16_t IPCIE:1; /* illegal protocol command interrupt enable */ 06660 vuint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */ 06661 vuint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */ 06662 vuint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */ 06663 vuint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */ 06664 vuint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */ 06665 vuint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */ 06666 vuint16_t:2; 06667 vuint16_t EVTIE:1; /* even cycle table written interrupt enable */ 06668 vuint16_t ODTIE:1; /* odd cycle table written interrupt enable */ 06669 vuint16_t:4; 06670 } B; 06671 } PIER1_t; 06672 typedef union uCHIERFR { 06673 vuint16_t R; 06674 struct { 06675 vuint16_t FRLBEF:1; /* flame lost channel B error flag */ 06676 vuint16_t FRLAEF:1; /* frame lost channel A error flag */ 06677 vuint16_t PCMIEF:1; /* command ignored error flag */ 06678 vuint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */ 06679 vuint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */ 06680 vuint16_t MSBEF:1; /* message buffer search error flag */ 06681 vuint16_t MBUEF:1; /* message buffer utilization error flag */ 06682 vuint16_t LCKEF:1; /* lock error flag */ 06683 vuint16_t DBLEF:1; /* double transmit message buffer lock error flag */ 06684 vuint16_t SBCFEF:1; /* system bus communication failure error flag */ 06685 vuint16_t FIDEF:1; /* frame ID error flag */ 06686 vuint16_t DPLEF:1; /* dynamic payload length error flag */ 06687 vuint16_t SPLEF:1; /* static payload length error flag */ 06688 vuint16_t NMLEF:1; /* network management length error flag */ 06689 vuint16_t NMFEF:1; /* network management frame error flag */ 06690 vuint16_t ILSAEF:1; /* illegal access error flag */ 06691 } B; 06692 } CHIERFR_t; 06693 typedef union uMBIVEC { 06694 vuint16_t R; 06695 struct { 06696 06697 vuint16_t:2; 06698 vuint16_t TBIVEC:6; /* transmit buffer interrupt vector */ 06699 vuint16_t:2; 06700 vuint16_t RBIVEC:6; /* receive buffer interrupt vector */ 06701 } B; 06702 } MBIVEC_t; 06703 06704 typedef union uPSR0 { 06705 vuint16_t R; 06706 struct { 06707 vuint16_t ERRMODE:2; /* error mode */ 06708 vuint16_t SLOTMODE:2; /* slot mode */ 06709 vuint16_t:1; 06710 vuint16_t PROTSTATE:3; /* protocol state */ 06711 vuint16_t SUBSTATE:4; /* protocol sub state */ 06712 vuint16_t:1; 06713 vuint16_t WAKEUPSTATUS:3; /* wakeup status */ 06714 } B; 06715 } PSR0_t; 06716 06717 /* protocol states */ 06718 /* protocol sub-states */ 06719 /* wakeup status */ 06720 typedef union uPSR1 { 06721 vuint16_t R; 06722 struct { 06723 vuint16_t CSAA:1; /* cold start attempt abort flag */ 06724 vuint16_t SCP:1; /* cold start path */ 06725 vuint16_t:1; 06726 vuint16_t REMCSAT:5; /* remanining coldstart attempts */ 06727 vuint16_t CPN:1; /* cold start noise path */ 06728 vuint16_t HHR:1; /* host halt request pending */ 06729 vuint16_t FRZ:1; /* freeze occured */ 06730 vuint16_t APTAC:5; /* allow passive to active counter */ 06731 } B; 06732 } PSR1_t; 06733 typedef union uPSR2 { 06734 vuint16_t R; 06735 struct { 06736 vuint16_t NBVB:1; /* NIT boundary violation on channel B */ 06737 vuint16_t NSEB:1; /* NIT syntax error on channel B */ 06738 vuint16_t STCB:1; /* symbol window transmit conflict on channel B */ 06739 vuint16_t SBVB:1; /* symbol window boundary violation on channel B */ 06740 vuint16_t SSEB:1; /* symbol window syntax error on channel B */ 06741 vuint16_t MTB:1; /* media access test symbol MTS received on channel B */ 06742 vuint16_t NBVA:1; /* NIT boundary violation on channel A */ 06743 vuint16_t NSEA:1; /* NIT syntax error on channel A */ 06744 vuint16_t STCA:1; /* symbol window transmit conflict on channel A */ 06745 vuint16_t SBVA:1; /* symbol window boundary violation on channel A */ 06746 vuint16_t SSEA:1; /* symbol window syntax error on channel A */ 06747 vuint16_t MTA:1; /* media access test symbol MTS received on channel A */ 06748 vuint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */ 06749 } B; 06750 } PSR2_t; 06751 typedef union uPSR3 { 06752 vuint16_t R; 06753 struct { 06754 vuint16_t:2; 06755 vuint16_t WUB:1; /* wakeup symbol received on channel B */ 06756 vuint16_t ABVB:1; /* aggregated boundary violation on channel B */ 06757 vuint16_t AACB:1; /* aggregated additional communication on channel B */ 06758 vuint16_t ACEB:1; /* aggregated content error on channel B */ 06759 vuint16_t ASEB:1; /* aggregated syntax error on channel B */ 06760 vuint16_t AVFB:1; /* aggregated valid frame on channel B */ 06761 vuint16_t:2; 06762 vuint16_t WUA:1; /* wakeup symbol received on channel A */ 06763 vuint16_t ABVA:1; /* aggregated boundary violation on channel A */ 06764 vuint16_t AACA:1; /* aggregated additional communication on channel A */ 06765 vuint16_t ACEA:1; /* aggregated content error on channel A */ 06766 vuint16_t ASEA:1; /* aggregated syntax error on channel A */ 06767 vuint16_t AVFA:1; /* aggregated valid frame on channel A */ 06768 } B; 06769 } PSR3_t; 06770 typedef union uCIFRR { 06771 vuint16_t R; 06772 struct { 06773 vuint16_t:8; 06774 vuint16_t MIFR:1; /* module interrupt flag */ 06775 vuint16_t PRIFR:1; /* protocol interrupt flag */ 06776 vuint16_t CHIFR:1; /* CHI interrupt flag */ 06777 vuint16_t WUPIFR:1; /* wakeup interrupt flag */ 06778 vuint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */ 06779 vuint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */ 06780 vuint16_t RBIFR:1; /* receive message buffer interrupt flag */ 06781 vuint16_t TBIFR:1; /* transmit buffer interrupt flag */ 06782 } B; 06783 } CIFRR_t; 06784 typedef union uSFCNTR { 06785 vuint16_t R; 06786 struct { 06787 vuint16_t SFEVB:4; /* sync frames channel B, even cycle */ 06788 vuint16_t SFEVA:4; /* sync frames channel A, even cycle */ 06789 vuint16_t SFODB:4; /* sync frames channel B, odd cycle */ 06790 vuint16_t SFODA:4; /* sync frames channel A, odd cycle */ 06791 } B; 06792 } SFCNTR_t; 06793 06794 typedef union uSFTCCSR { 06795 vuint16_t R; 06796 struct { 06797 vuint16_t ELKT:1; /* even cycle tables lock and unlock trigger */ 06798 vuint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */ 06799 vuint16_t CYCNUM:6; /* cycle number */ 06800 vuint16_t ELKS:1; /* even cycle tables lock status */ 06801 vuint16_t OLKS:1; /* odd cycle tables lock status */ 06802 vuint16_t EVAL:1; /* even cycle tables valid */ 06803 vuint16_t OVAL:1; /* odd cycle tables valid */ 06804 vuint16_t:1; 06805 vuint16_t OPT:1; /*one pair trigger */ 06806 vuint16_t SDVEN:1; /* sync frame deviation table enable */ 06807 vuint16_t SIDEN:1; /* sync frame ID table enable */ 06808 } B; 06809 } SFTCCSR_t; 06810 typedef union uSFIDRFR { 06811 vuint16_t R; 06812 struct { 06813 vuint16_t:6; 06814 vuint16_t SYNFRID:10; /* sync frame rejection ID */ 06815 } B; 06816 } SFIDRFR_t; 06817 06818 typedef union uTICCR { 06819 vuint16_t R; 06820 struct { 06821 vuint16_t:2; 06822 vuint16_t T2CFG:1; /* timer 2 configuration */ 06823 vuint16_t T2REP:1; /* timer 2 repetitive mode */ 06824 vuint16_t:1; 06825 vuint16_t T2SP:1; /* timer 2 stop */ 06826 vuint16_t T2TR:1; /* timer 2 trigger */ 06827 vuint16_t T2ST:1; /* timer 2 state */ 06828 vuint16_t:3; 06829 vuint16_t T1REP:1; /* timer 1 repetitive mode */ 06830 vuint16_t:1; 06831 vuint16_t T1SP:1; /* timer 1 stop */ 06832 vuint16_t T1TR:1; /* timer 1 trigger */ 06833 vuint16_t T1ST:1; /* timer 1 state */ 06834 06835 } B; 06836 } TICCR_t; 06837 typedef union uTI1CYSR { 06838 vuint16_t R; 06839 struct { 06840 vuint16_t:2; 06841 vuint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */ 06842 vuint16_t:2; 06843 vuint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */ 06844 06845 } B; 06846 } TI1CYSR_t; 06847 06848 typedef union uSSSR { 06849 vuint16_t R; 06850 struct { 06851 vuint16_t WMD:1; /* write mode */ 06852 vuint16_t:1; 06853 vuint16_t SEL:2; /* static slot number */ 06854 vuint16_t:1; 06855 vuint16_t SLOTNUMBER:11; /* selector */ 06856 } B; 06857 } SSSR_t; 06858 06859 typedef union uSSCCR { 06860 vuint16_t R; 06861 struct { 06862 vuint16_t WMD:1; /* write mode */ 06863 vuint16_t:1; 06864 vuint16_t SEL:2; /* selector */ 06865 vuint16_t:1; 06866 vuint16_t CNTCFG:2; /* counter configuration */ 06867 vuint16_t MCY:1; /* multi cycle selection */ 06868 vuint16_t VFR:1; /* valid frame selection */ 06869 vuint16_t SYF:1; /* sync frame selection */ 06870 vuint16_t NUF:1; /* null frame selection */ 06871 vuint16_t SUF:1; /* startup frame selection */ 06872 vuint16_t STATUSMASK:4; /* slot status mask */ 06873 } B; 06874 } SSCCR_t; 06875 typedef union uSSR { 06876 vuint16_t R; 06877 struct { 06878 vuint16_t VFB:1; /* valid frame on channel B */ 06879 vuint16_t SYB:1; /* valid sync frame on channel B */ 06880 vuint16_t NFB:1; /* valid null frame on channel B */ 06881 vuint16_t SUB:1; /* valid startup frame on channel B */ 06882 vuint16_t SEB:1; /* syntax error on channel B */ 06883 vuint16_t CEB:1; /* content error on channel B */ 06884 vuint16_t BVB:1; /* boundary violation on channel B */ 06885 vuint16_t TCB:1; /* tx conflict on channel B */ 06886 vuint16_t VFA:1; /* valid frame on channel A */ 06887 vuint16_t SYA:1; /* valid sync frame on channel A */ 06888 vuint16_t NFA:1; /* valid null frame on channel A */ 06889 vuint16_t SUA:1; /* valid startup frame on channel A */ 06890 vuint16_t SEA:1; /* syntax error on channel A */ 06891 vuint16_t CEA:1; /* content error on channel A */ 06892 vuint16_t BVA:1; /* boundary violation on channel A */ 06893 vuint16_t TCA:1; /* tx conflict on channel A */ 06894 } B; 06895 } SSR_t; 06896 typedef union uMTSCFR { 06897 vuint16_t R; 06898 struct { 06899 vuint16_t MTE:1; /* media access test symbol transmission enable */ 06900 vuint16_t:1; 06901 vuint16_t CYCCNTMSK:6; /* cycle counter mask */ 06902 vuint16_t:2; 06903 vuint16_t CYCCNTVAL:6; /* cycle counter value */ 06904 } B; 06905 } MTSCFR_t; 06906 06907 typedef union uRSBIR { 06908 vuint16_t R; 06909 struct { 06910 vuint16_t WMD:1; /* write mode */ 06911 vuint16_t:1; 06912 vuint16_t SEL:2; /* selector */ 06913 vuint16_t:5; 06914 vuint16_t RSBIDX:7; /* receive shadow buffer index */ 06915 } B; 06916 } RSBIR_t; 06917 06918 typedef union uRFDSR { 06919 vuint16_t R; 06920 struct { 06921 vuint16_t FIFODEPTH:8; /* fifo depth */ 06922 vuint16_t:1; 06923 vuint16_t ENTRYSIZE:7; /* entry size */ 06924 } B; 06925 } RFDSR_t; 06926 06927 typedef union uRFRFCFR { 06928 vuint16_t R; 06929 struct { 06930 vuint16_t WMD:1; /* write mode */ 06931 vuint16_t IBD:1; /* interval boundary */ 06932 vuint16_t SEL:2; /* filter number */ 06933 vuint16_t:1; 06934 vuint16_t SID:11; /* slot ID */ 06935 } B; 06936 } RFRFCFR_t; 06937 06938 typedef union uRFRFCTR { 06939 vuint16_t R; 06940 struct { 06941 vuint16_t:4; 06942 vuint16_t F3MD:1; /* filter mode */ 06943 vuint16_t F2MD:1; /* filter mode */ 06944 vuint16_t F1MD:1; /* filter mode */ 06945 vuint16_t F0MD:1; /* filter mode */ 06946 vuint16_t:4; 06947 vuint16_t F3EN:1; /* filter enable */ 06948 vuint16_t F2EN:1; /* filter enable */ 06949 vuint16_t F1EN:1; /* filter enable */ 06950 vuint16_t F0EN:1; /* filter enable */ 06951 } B; 06952 } RFRFCTR_t; 06953 typedef union uPCR0 { 06954 vuint16_t R; 06955 struct { 06956 vuint16_t ACTION_POINT_OFFSET:6; 06957 vuint16_t STATIC_SLOT_LENGTH:10; 06958 } B; 06959 } PCR0_t; 06960 06961 typedef union uPCR1 { 06962 vuint16_t R; 06963 struct { 06964 vuint16_t:2; 06965 vuint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14; 06966 } B; 06967 } PCR1_t; 06968 06969 typedef union uPCR2 { 06970 vuint16_t R; 06971 struct { 06972 vuint16_t MINISLOT_AFTER_ACTION_POINT:6; 06973 vuint16_t NUMBER_OF_STATIC_SLOTS:10; 06974 } B; 06975 } PCR2_t; 06976 06977 typedef union uPCR3 { 06978 vuint16_t R; 06979 struct { 06980 vuint16_t WAKEUP_SYMBOL_RX_LOW:6; 06981 vuint16_t MINISLOT_ACTION_POINT_OFFSET:5; 06982 vuint16_t COLDSTART_ATTEMPTS:5; 06983 } B; 06984 } PCR3_t; 06985 06986 typedef union uPCR4 { 06987 vuint16_t R; 06988 struct { 06989 vuint16_t CAS_RX_LOW_MAX:7; 06990 vuint16_t WAKEUP_SYMBOL_RX_WINDOW:9; 06991 } B; 06992 } PCR4_t; 06993 06994 typedef union uPCR5 { 06995 vuint16_t R; 06996 struct { 06997 vuint16_t TSS_TRANSMITTER:4; 06998 vuint16_t WAKEUP_SYMBOL_TX_LOW:6; 06999 vuint16_t WAKEUP_SYMBOL_RX_IDLE:6; 07000 } B; 07001 } PCR5_t; 07002 07003 typedef union uPCR6 { 07004 vuint16_t R; 07005 struct { 07006 vuint16_t:1; 07007 vuint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8; 07008 vuint16_t MACRO_INITIAL_OFFSET_A:7; 07009 } B; 07010 } PCR6_t; 07011 07012 typedef union uPCR7 { 07013 vuint16_t R; 07014 struct { 07015 vuint16_t DECODING_CORRECTION_B:9; 07016 vuint16_t MICRO_PER_MACRO_NOM_HALF:7; 07017 } B; 07018 } PCR7_t; 07019 07020 typedef union uPCR8 { 07021 vuint16_t R; 07022 struct { 07023 vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4; 07024 vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4; 07025 vuint16_t WAKEUP_SYMBOL_TX_IDLE:8; 07026 } B; 07027 } PCR8_t; 07028 07029 typedef union uPCR9 { 07030 vuint16_t R; 07031 struct { 07032 vuint16_t MINISLOT_EXISTS:1; 07033 vuint16_t SYMBOL_WINDOW_EXISTS:1; 07034 vuint16_t OFFSET_CORRECTION_OUT:14; 07035 } B; 07036 } PCR9_t; 07037 07038 typedef union uPCR10 { 07039 vuint16_t R; 07040 struct { 07041 vuint16_t SINGLE_SLOT_ENABLED:1; 07042 vuint16_t WAKEUP_CHANNEL:1; 07043 vuint16_t MACRO_PER_CYCLE:14; 07044 } B; 07045 } PCR10_t; 07046 07047 typedef union uPCR11 { 07048 vuint16_t R; 07049 struct { 07050 vuint16_t KEY_SLOT_USED_FOR_STARTUP:1; 07051 vuint16_t KEY_SLOT_USED_FOR_SYNC:1; 07052 vuint16_t OFFSET_CORRECTION_START:14; 07053 } B; 07054 } PCR11_t; 07055 07056 typedef union uPCR12 { 07057 vuint16_t R; 07058 struct { 07059 vuint16_t ALLOW_PASSIVE_TO_ACTIVE:5; 07060 vuint16_t KEY_SLOT_HEADER_CRC:11; 07061 } B; 07062 } PCR12_t; 07063 07064 typedef union uPCR13 { 07065 vuint16_t R; 07066 struct { 07067 vuint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6; 07068 vuint16_t STATIC_SLOT_AFTER_ACTION_POINT:10; 07069 } B; 07070 } PCR13_t; 07071 07072 typedef union uPCR14 { 07073 vuint16_t R; 07074 struct { 07075 vuint16_t RATE_CORRECTION_OUT:11; 07076 vuint16_t LISTEN_TIMEOUT_H:5; 07077 } B; 07078 } PCR14_t; 07079 07080 typedef union uPCR15 { 07081 vuint16_t R; 07082 struct { 07083 vuint16_t LISTEN_TIMEOUT_L:16; 07084 } B; 07085 } PCR15_t; 07086 07087 typedef union uPCR16 { 07088 vuint16_t R; 07089 struct { 07090 vuint16_t MACRO_INITIAL_OFFSET_B:7; 07091 vuint16_t NOISE_LISTEN_TIMEOUT_H:9; 07092 } B; 07093 } PCR16_t; 07094 07095 typedef union uPCR17 { 07096 vuint16_t R; 07097 struct { 07098 vuint16_t NOISE_LISTEN_TIMEOUT_L:16; 07099 } B; 07100 } PCR17_t; 07101 07102 typedef union uPCR18 { 07103 vuint16_t R; 07104 struct { 07105 vuint16_t WAKEUP_PATTERN:6; 07106 vuint16_t KEY_SLOT_ID:10; 07107 } B; 07108 } PCR18_t; 07109 07110 typedef union uPCR19 { 07111 vuint16_t R; 07112 struct { 07113 vuint16_t DECODING_CORRECTION_A:9; 07114 vuint16_t PAYLOAD_LENGTH_STATIC:7; 07115 } B; 07116 } PCR19_t; 07117 07118 typedef union uPCR20 { 07119 vuint16_t R; 07120 struct { 07121 vuint16_t MICRO_INITIAL_OFFSET_B:8; 07122 vuint16_t MICRO_INITIAL_OFFSET_A:8; 07123 } B; 07124 } PCR20_t; 07125 07126 typedef union uPCR21 { 07127 vuint16_t R; 07128 struct { 07129 vuint16_t EXTERN_RATE_CORRECTION:3; 07130 vuint16_t LATEST_TX:13; 07131 } B; 07132 } PCR21_t; 07133 07134 typedef union uPCR22 { 07135 vuint16_t R; 07136 struct { 07137 vuint16_t:1; 07138 vuint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11; 07139 vuint16_t MICRO_PER_CYCLE_H:4; 07140 } B; 07141 } PCR22_t; 07142 07143 typedef union uPCR23 { 07144 vuint16_t R; 07145 struct { 07146 vuint16_t micro_per_cycle_l:16; 07147 } B; 07148 } PCR23_t; 07149 07150 typedef union uPCR24 { 07151 vuint16_t R; 07152 struct { 07153 vuint16_t CLUSTER_DRIFT_DAMPING:5; 07154 vuint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7; 07155 vuint16_t MICRO_PER_CYCLE_MIN_H:4; 07156 } B; 07157 } PCR24_t; 07158 07159 typedef union uPCR25 { 07160 vuint16_t R; 07161 struct { 07162 vuint16_t MICRO_PER_CYCLE_MIN_L:16; 07163 } B; 07164 } PCR25_t; 07165 07166 typedef union uPCR26 { 07167 vuint16_t R; 07168 struct { 07169 vuint16_t ALLOW_HALT_DUE_TO_CLOCK:1; 07170 vuint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11; 07171 vuint16_t MICRO_PER_CYCLE_MAX_H:4; 07172 } B; 07173 } PCR26_t; 07174 07175 typedef union uPCR27 { 07176 vuint16_t R; 07177 struct { 07178 vuint16_t MICRO_PER_CYCLE_MAX_L:16; 07179 } B; 07180 } PCR27_t; 07181 07182 typedef union uPCR28 { 07183 vuint16_t R; 07184 struct { 07185 vuint16_t DYNAMIC_SLOT_IDLE_PHASE:2; 07186 vuint16_t MACRO_AFTER_OFFSET_CORRECTION:14; 07187 } B; 07188 } PCR28_t; 07189 07190 typedef union uPCR29 { 07191 vuint16_t R; 07192 struct { 07193 vuint16_t EXTERN_OFFSET_CORRECTION:3; 07194 vuint16_t MINISLOTS_MAX:13; 07195 } B; 07196 } PCR29_t; 07197 07198 typedef union uPCR30 { 07199 vuint16_t R; 07200 struct { 07201 vuint16_t:12; 07202 vuint16_t SYNC_NODE_MAX:4; 07203 } B; 07204 } PCR30_t; 07205 07206 typedef struct uMSG_BUFF_CCS { 07207 union { 07208 vuint16_t R; 07209 struct { 07210 vuint16_t:1; 07211 vuint16_t MCM:1; /* message buffer commit mode */ 07212 vuint16_t MBT:1; /* message buffer type */ 07213 vuint16_t MTD:1; /* message buffer direction */ 07214 vuint16_t CMT:1; /* commit for transmission */ 07215 vuint16_t EDT:1; /* enable / disable trigger */ 07216 vuint16_t LCKT:1; /* lock request trigger */ 07217 vuint16_t MBIE:1; /* message buffer interrupt enable */ 07218 vuint16_t:3; 07219 vuint16_t DUP:1; /* data updated */ 07220 vuint16_t DVAL:1; /* data valid */ 07221 vuint16_t EDS:1; /* lock status */ 07222 vuint16_t LCKS:1; /* enable / disable status */ 07223 vuint16_t MBIF:1; /* message buffer interrupt flag */ 07224 } B; 07225 } MBCCSR; 07226 union { 07227 vuint16_t R; 07228 struct { 07229 vuint16_t MTM:1; /* message buffer transmission mode */ 07230 vuint16_t CHNLA:1; /* channel assignement */ 07231 vuint16_t CHNLB:1; /* channel assignement */ 07232 vuint16_t CCFE:1; /* cycle counter filter enable */ 07233 vuint16_t CCFMSK:6; /* cycle counter filter mask */ 07234 vuint16_t CCFVAL:6; /* cycle counter filter value */ 07235 } B; 07236 } MBCCFR; 07237 union { 07238 vuint16_t R; 07239 struct { 07240 vuint16_t:5; 07241 vuint16_t FID:11; /* frame ID */ 07242 } B; 07243 } MBFIDR; 07244 07245 union { 07246 vuint16_t R; 07247 struct { 07248 vuint16_t:9; 07249 vuint16_t MBIDX:7; /* message buffer index */ 07250 } B; 07251 } MBIDXR; 07252 } MSG_BUFF_CCS_t; 07253 typedef union uSYSBADHR { 07254 vuint16_t R; 07255 } SYSBADHR_t; 07256 typedef union uSYSBADLR { 07257 vuint16_t R; 07258 } SYSBADLR_t; 07259 typedef union uPADR { 07260 vuint16_t R; 07261 } PADR_t; 07262 typedef union uPDAR { 07263 vuint16_t R; 07264 } PDAR_t; 07265 typedef union uCASERCR { 07266 vuint16_t R; 07267 } CASERCR_t; 07268 typedef union uCBSERCR { 07269 vuint16_t R; 07270 } CBSERCR_t; 07271 typedef union uCYCTR { 07272 vuint16_t R; 07273 } CYCTR_t; 07274 typedef union uMTCTR { 07275 vuint16_t R; 07276 } MTCTR_t; 07277 typedef union uSLTCTAR { 07278 vuint16_t R; 07279 } SLTCTAR_t; 07280 typedef union uSLTCTBR { 07281 vuint16_t R; 07282 } SLTCTBR_t; 07283 typedef union uRTCORVR { 07284 vuint16_t R; 07285 } RTCORVR_t; 07286 typedef union uOFCORVR { 07287 vuint16_t R; 07288 } OFCORVR_t; 07289 typedef union uSFTOR { 07290 vuint16_t R; 07291 } SFTOR_t; 07292 typedef union uSFIDAFVR { 07293 vuint16_t R; 07294 } SFIDAFVR_t; 07295 typedef union uSFIDAFMR { 07296 vuint16_t R; 07297 } SFIDAFMR_t; 07298 typedef union uNMVR { 07299 vuint16_t R; 07300 } NMVR_t; 07301 typedef union uNMVLR { 07302 vuint16_t R; 07303 } NMVLR_t; 07304 typedef union uT1MTOR { 07305 vuint16_t R; 07306 } T1MTOR_t; 07307 typedef union uTI2CR0 { 07308 vuint16_t R; 07309 } TI2CR0_t; 07310 typedef union uTI2CR1 { 07311 vuint16_t R; 07312 } TI2CR1_t; 07313 typedef union uSSCR { 07314 vuint16_t R; 07315 } SSCR_t; 07316 typedef union uRFSR { 07317 vuint16_t R; 07318 } RFSR_t; 07319 typedef union uRFSIR { 07320 vuint16_t R; 07321 } RFSIR_t; 07322 typedef union uRFARIR { 07323 vuint16_t R; 07324 } RFARIR_t; 07325 typedef union uRFBRIR { 07326 vuint16_t R; 07327 } RFBRIR_t; 07328 typedef union uRFMIDAFVR { 07329 vuint16_t R; 07330 } RFMIDAFVR_t; 07331 typedef union uRFMIAFMR { 07332 vuint16_t R; 07333 } RFMIAFMR_t; 07334 typedef union uRFFIDRFVR { 07335 vuint16_t R; 07336 } RFFIDRFVR_t; 07337 typedef union uRFFIDRFMR { 07338 vuint16_t R; 07339 } RFFIDRFMR_t; 07340 typedef union uLDTXSLAR { 07341 vuint16_t R; 07342 } LDTXSLAR_t; 07343 typedef union uLDTXSLBR { 07344 vuint16_t R; 07345 } LDTXSLBR_t; 07346 07347 typedef struct FR_tag { 07348 volatile MVR_t MVR; /*module version register *//*0 */ 07349 volatile MCR_t MCR; /*module configuration register *//*2 */ 07350 volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */ 07351 volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */ 07352 volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */ 07353 volatile STBPCR_t STBPCR; /*strobe port control register *//*A */ 07354 volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */ 07355 volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */ 07356 volatile PADR_t PADR; /*PE address register *//*10 */ 07357 volatile PDAR_t PDAR; /*PE data register *//*12 */ 07358 volatile POCR_t POCR; /*Protocol operation control register *//*14 */ 07359 volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */ 07360 volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */ 07361 volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */ 07362 volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */ 07363 volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */ 07364 volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */ 07365 volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */ 07366 volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */ 07367 volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */ 07368 volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */ 07369 volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */ 07370 volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */ 07371 volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */ 07372 volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */ 07373 volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */ 07374 volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */ 07375 volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */ 07376 volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */ 07377 volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */ 07378 volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */ 07379 vuint16_t reserved3[1]; /*3E */ 07380 volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */ 07381 volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */ 07382 volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */ 07383 volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */ 07384 volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */ 07385 volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */ 07386 volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */ 07387 volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */ 07388 volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */ 07389 volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */ 07390 volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */ 07391 volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */ 07392 volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */ 07393 volatile SSSR_t SSSR; /*slot status selection register *//*64 */ 07394 volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */ 07395 volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */ 07396 volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */ 07397 volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */ 07398 volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */ 07399 volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */ 07400 volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */ 07401 volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */ 07402 volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */ 07403 volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */ 07404 volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */ 07405 volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */ 07406 volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */ 07407 volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */ 07408 volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */ 07409 volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */ 07410 volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */ 07411 volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */ 07412 volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */ 07413 volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */ 07414 volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */ 07415 volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */ 07416 volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */ 07417 volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */ 07418 volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */ 07419 volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */ 07420 volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */ 07421 volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */ 07422 volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */ 07423 volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */ 07424 volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */ 07425 volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */ 07426 volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */ 07427 volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */ 07428 volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */ 07429 volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */ 07430 volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */ 07431 volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */ 07432 volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */ 07433 volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */ 07434 volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */ 07435 volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */ 07436 volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */ 07437 volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */ 07438 volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */ 07439 volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */ 07440 volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */ 07441 volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */ 07442 volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */ 07443 volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */ 07444 vuint16_t reserved2[17]; 07445 volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */ 07446 } FR_tag_t; 07447 07448 typedef union uF_HEADER /* frame header */ 07449 { 07450 struct { 07451 vuint16_t:5; 07452 vuint16_t HDCRC:11; /* Header CRC */ 07453 vuint16_t:2; 07454 vuint16_t CYCCNT:6; /* Cycle Count */ 07455 vuint16_t:1; 07456 vuint16_t PLDLEN:7; /* Payload Length */ 07457 vuint16_t:1; 07458 vuint16_t PPI:1; /* Payload Preamble Indicator */ 07459 vuint16_t NUF:1; /* Null Frame Indicator */ 07460 vuint16_t SYF:1; /* Sync Frame Indicator */ 07461 vuint16_t SUF:1; /* Startup Frame Indicator */ 07462 vuint16_t FID:11; /* Frame ID */ 07463 } B; 07464 vuint16_t WORDS[3]; 07465 } F_HEADER_t; 07466 typedef union uS_STSTUS /* slot status */ 07467 { 07468 struct { 07469 vuint16_t VFB:1; /* Valid Frame on channel B */ 07470 vuint16_t SYB:1; /* Sync Frame Indicator channel B */ 07471 vuint16_t NFB:1; /* Null Frame Indicator channel B */ 07472 vuint16_t SUB:1; /* Startup Frame Indicator channel B */ 07473 vuint16_t SEB:1; /* Syntax Error on channel B */ 07474 vuint16_t CEB:1; /* Content Error on channel B */ 07475 vuint16_t BVB:1; /* Boundary Violation on channel B */ 07476 vuint16_t CH:1; /* Channel */ 07477 vuint16_t VFA:1; /* Valid Frame on channel A */ 07478 vuint16_t SYA:1; /* Sync Frame Indicator channel A */ 07479 vuint16_t NFA:1; /* Null Frame Indicator channel A */ 07480 vuint16_t SUA:1; /* Startup Frame Indicator channel A */ 07481 vuint16_t SEA:1; /* Syntax Error on channel A */ 07482 vuint16_t CEA:1; /* Content Error on channel A */ 07483 vuint16_t BVA:1; /* Boundary Violation on channel A */ 07484 vuint16_t:1; 07485 } RX; 07486 struct { 07487 vuint16_t VFB:1; /* Valid Frame on channel B */ 07488 vuint16_t SYB:1; /* Sync Frame Indicator channel B */ 07489 vuint16_t NFB:1; /* Null Frame Indicator channel B */ 07490 vuint16_t SUB:1; /* Startup Frame Indicator channel B */ 07491 vuint16_t SEB:1; /* Syntax Error on channel B */ 07492 vuint16_t CEB:1; /* Content Error on channel B */ 07493 vuint16_t BVB:1; /* Boundary Violation on channel B */ 07494 vuint16_t TCB:1; /* Tx Conflict on channel B */ 07495 vuint16_t VFA:1; /* Valid Frame on channel A */ 07496 vuint16_t SYA:1; /* Sync Frame Indicator channel A */ 07497 vuint16_t NFA:1; /* Null Frame Indicator channel A */ 07498 vuint16_t SUA:1; /* Startup Frame Indicator channel A */ 07499 vuint16_t SEA:1; /* Syntax Error on channel A */ 07500 vuint16_t CEA:1; /* Content Error on channel A */ 07501 vuint16_t BVA:1; /* Boundary Violation on channel A */ 07502 vuint16_t TCA:1; /* Tx Conflict on channel A */ 07503 } TX; 07504 vuint16_t R; 07505 } S_STATUS_t; 07506 07507 typedef struct uMB_HEADER /* message buffer header */ 07508 { 07509 F_HEADER_t FRAME_HEADER; 07510 vuint16_t DATA_OFFSET; 07511 S_STATUS_t SLOT_STATUS; 07512 } MB_HEADER_t; 07513 /****************************************************************************/ 07514 /* MODULE : LCD */ 07515 /****************************************************************************/ 07516 struct LCD_tag { 07517 07518 union { 07519 vuint32_t R; 07520 struct { 07521 vuint32_t LCDEN:1; 07522 vuint32_t LCDRST:1; 07523 vuint32_t LCDRCS:1; 07524 vuint32_t DUTY:3; 07525 vuint32_t BIAS:1; 07526 vuint32_t VLCDS:1; 07527 vuint32_t PWR:2; 07528 vuint32_t BSTEN:1; 07529 vuint32_t BSTSEL:1; 07530 vuint32_t BSTAO:1; 07531 vuint32_t:1; 07532 vuint32_t LCDINT:1; 07533 vuint32_t EOFF:1; 07534 vuint32_t NOF:8; 07535 vuint32_t:2; 07536 vuint32_t LCDBPA:1; 07537 vuint32_t:2; 07538 vuint32_t LCDBPS:3; 07539 } B; 07540 } CR; /* LCD Control Register */ 07541 07542 union { 07543 vuint32_t R; 07544 struct { 07545 vuint32_t:4; 07546 vuint32_t LCLK:4; 07547 vuint32_t:24; 07548 } B; 07549 } PCR; /* LCD Prescaler Control Register */ 07550 07551 union { 07552 vuint32_t R; 07553 struct { 07554 vuint32_t CCEN:1; 07555 vuint32_t:4; 07556 vuint32_t LCC:11; 07557 vuint32_t:16; 07558 } B; 07559 } CCR; /* LCD Contrast Control Register */ 07560 07561 int32_t LCD_reserved1; /* (0x10 - 0x0C)/4 = 0x01 */ 07562 07563 union { 07564 vuint32_t R; 07565 struct { 07566 vuint32_t FP31EN:1; 07567 vuint32_t FP30EN:1; 07568 vuint32_t FP29EN:1; 07569 vuint32_t FP28EN:1; 07570 vuint32_t FP27EN:1; 07571 vuint32_t FP26EN:1; 07572 vuint32_t FP25EN:1; 07573 vuint32_t FP24EN:1; 07574 vuint32_t FP23EN:1; 07575 vuint32_t FP22EN:1; 07576 vuint32_t FP21EN:1; 07577 vuint32_t FP20EN:1; 07578 vuint32_t FP19EN:1; 07579 vuint32_t FP18EN:1; 07580 vuint32_t FP17EN:1; 07581 vuint32_t FP16EN:1; 07582 vuint32_t FP15EN:1; 07583 vuint32_t FP14EN:1; 07584 vuint32_t FP13EN:1; 07585 vuint32_t FP12EN:1; 07586 vuint32_t FP11EN:1; 07587 vuint32_t FP10EN:1; 07588 vuint32_t FP9EN:1; 07589 vuint32_t FP8EN:1; 07590 vuint32_t FP7EN:1; 07591 vuint32_t FP6EN:1; 07592 vuint32_t FP5EN:1; 07593 vuint32_t FP4EN:1; 07594 vuint32_t FP3EN:1; 07595 vuint32_t FP2EN:1; 07596 vuint32_t FP1EN:1; 07597 vuint32_t FP0EN:1; 07598 } B; 07599 } FPENR0; /* LCD Frontplane Enable Register 0 */ 07600 07601 union { 07602 vuint32_t R; 07603 struct { 07604 vuint32_t FP63EN:1; 07605 vuint32_t FP62EN:1; 07606 vuint32_t FP61EN:1; 07607 vuint32_t FP60EN:1; 07608 vuint32_t FP59EN:1; 07609 vuint32_t FP58EN:1; 07610 vuint32_t FP57EN:1; 07611 vuint32_t FP56EN:1; 07612 vuint32_t FP55EN:1; 07613 vuint32_t FP54EN:1; 07614 vuint32_t FP53EN:1; 07615 vuint32_t FP52EN:1; 07616 vuint32_t FP51EN:1; 07617 vuint32_t FP50EN:1; 07618 vuint32_t FP49EN:1; 07619 vuint32_t FP48EN:1; 07620 vuint32_t FP47EN:1; 07621 vuint32_t FP46EN:1; 07622 vuint32_t FP45EN:1; 07623 vuint32_t FP44EN:1; 07624 vuint32_t FP43EN:1; 07625 vuint32_t FP42EN:1; 07626 vuint32_t FP41EN:1; 07627 vuint32_t FP40EN:1; 07628 vuint32_t FP39EN:1; 07629 vuint32_t FP38EN:1; 07630 vuint32_t FP37EN:1; 07631 vuint32_t FP36EN:1; 07632 vuint32_t FP35EN:1; 07633 vuint32_t FP34EN:1; 07634 vuint32_t FP33EN:1; 07635 vuint32_t FP32EN:1; 07636 } B; 07637 } FPENR1; /* LCD Frontplane Enable Register 1 */ 07638 07639 int32_t LCD_reserved2[2]; /* (0x20 - 0x18)/4 = 0x02 */ 07640 07641 union { 07642 vuint32_t R; 07643 } RAM[16]; /* LCD RAM Register */ 07644 07645 }; /* end of LCD_tag */ 07646 /****************************************************************************/ 07647 /* MODULE : External Bus Interface (EBI) */ 07648 /****************************************************************************/ 07649 struct EBI_CS_tag { 07650 union { /* Base Register Bank */ 07651 vuint32_t R; 07652 struct { 07653 vuint32_t BA:17; 07654 vuint32_t:3; 07655 vuint32_t PS:1; 07656 vuint32_t:4; 07657 vuint32_t BL:1; 07658 vuint32_t WEBS:1; 07659 vuint32_t TBDIP:1; 07660 vuint32_t:2; 07661 vuint32_t BI:1; 07662 vuint32_t V:1; 07663 } B; 07664 } BR; 07665 07666 union { /* Option Register Bank */ 07667 vuint32_t R; 07668 struct { 07669 vuint32_t AM:17; 07670 vuint32_t:7; 07671 vuint32_t SCY:4; 07672 vuint32_t:1; 07673 vuint32_t BSCY:2; 07674 vuint32_t:1; 07675 } B; 07676 } OR; 07677 }; /* end of EBI_CS_tag */ 07678 07679 struct EBI_tag { 07680 union { /* Module Configuration Register */ 07681 vuint32_t R; 07682 struct { 07683 vuint32_t:5; 07684 vuint32_t SIZEN:1; 07685 vuint32_t SIZE:2; 07686 vuint32_t:8; 07687 vuint32_t ACGE:1; 07688 vuint32_t EXTM:1; 07689 vuint32_t EARB:1; 07690 vuint32_t EARP:2; 07691 vuint32_t:4; 07692 vuint32_t MDIS:1; 07693 vuint32_t:4; 07694 vuint32_t AD_MUX:1; 07695 vuint32_t DBM:1; 07696 } B; 07697 } MCR; 07698 07699 uint32_t EBI_reserved1; 07700 07701 union { /* Transfer Error Status Register */ 07702 vuint32_t R; 07703 struct { 07704 vuint32_t:30; 07705 vuint32_t TEAF:1; 07706 vuint32_t BMTF:1; 07707 } B; 07708 } TESR; 07709 07710 union { /* Bus Monitor Control Register */ 07711 vuint32_t R; 07712 struct { 07713 vuint32_t:16; 07714 vuint32_t BMT:8; 07715 vuint32_t BME:1; 07716 vuint32_t:7; 07717 } B; 07718 } BMCR; 07719 07720 struct EBI_CS_tag CS[2]; 07721 07722 }; /* end of EBI_tag */ 07723 /****************************************************************************/ 07724 /* MODULE : DFLASH */ 07725 /****************************************************************************/ 07726 struct DFLASH_tag { 07727 union { /* Module Configuration Register */ 07728 vuint32_t R; 07729 struct { 07730 vuint32_t EDC:1; 07731 vuint32_t:4; 07732 vuint32_t SIZE:3; 07733 vuint32_t:1; 07734 vuint32_t LAS:3; 07735 vuint32_t:3; 07736 vuint32_t MAS:1; 07737 vuint32_t EER:1; 07738 vuint32_t RWE:1; 07739 vuint32_t:1; 07740 vuint32_t:1; 07741 vuint32_t PEAS:1; 07742 vuint32_t DONE:1; 07743 vuint32_t PEG:1; 07744 vuint32_t:4; 07745 vuint32_t PGM:1; 07746 vuint32_t PSUS:1; 07747 vuint32_t ERS:1; 07748 vuint32_t ESUS:1; 07749 vuint32_t EHV:1; 07750 } B; 07751 } MCR; 07752 07753 union { /* LML Register */ 07754 vuint32_t R; 07755 struct { 07756 vuint32_t LME:1; 07757 vuint32_t:10; 07758 vuint32_t TSLK:1; 07759 vuint32_t:2; 07760 vuint32_t MLK:2; 07761 vuint32_t LLK:16; 07762 } B; 07763 } LML; 07764 07765 union { /* HBL Register */ 07766 vuint32_t R; 07767 struct { 07768 vuint32_t HBE:1; 07769 vuint32_t:23; 07770 vuint32_t HBLOCK:8; 07771 } B; 07772 } HBL; 07773 07774 union { /* SLML Register */ 07775 vuint32_t R; 07776 struct { 07777 vuint32_t SLE:1; 07778 vuint32_t:10; 07779 vuint32_t STSLK:1; 07780 vuint32_t:2; 07781 vuint32_t SMK:2; 07782 vuint32_t SLK:16; 07783 } B; 07784 } SLL; 07785 07786 union { /* LMS Register */ 07787 vuint32_t R; 07788 struct { 07789 vuint32_t:14; 07790 vuint32_t MSL:2; 07791 vuint32_t LSL:16; 07792 } B; 07793 } LMS; 07794 07795 union { /* High Address Space Block Select Register */ 07796 vuint32_t R; 07797 struct { 07798 vuint32_t:26; 07799 vuint32_t HSL:6; 07800 } B; 07801 } HBS; 07802 07803 union { /* Address Register */ 07804 vuint32_t R; 07805 struct { 07806 vuint32_t:9; 07807 vuint32_t ADD:20; 07808 vuint32_t:3; 07809 } B; 07810 } ADR; 07811 07812 int32_t Dflash_reserved0[8]; /* {0x003C-0x001C}/0x4 = 0x08 */ 07813 07814 union { /* User Test Register 0 */ 07815 vuint32_t R; 07816 struct { 07817 vuint32_t UTE:1; 07818 vuint32_t:7; 07819 vuint32_t DSI:8; 07820 vuint32_t:10; 07821 vuint32_t MRE:1; 07822 vuint32_t MRV:1; 07823 vuint32_t EIE:1; 07824 vuint32_t AIS:1; 07825 vuint32_t AIE:1; 07826 vuint32_t AID:1; 07827 } B; 07828 } UT0; 07829 07830 union { /* User Test Register 1 */ 07831 vuint32_t R; 07832 struct { 07833 vuint32_t DAI:32; 07834 } B; 07835 } UT1; 07836 07837 union { /* User Test Register 2 */ 07838 vuint32_t R; 07839 struct { 07840 vuint32_t DAI:32; 07841 } B; 07842 } UT2; 07843 07844 union { /* User Multiple Input Signature Register 0-4 */ 07845 vuint32_t R; 07846 struct { 07847 vuint32_t MS:32; 07848 } B; 07849 } UMISR[5]; 07850 07851 }; /* end of Dflash_tag */ 07852 /****************************************************************************/ 07853 /* MODULE : CFLASH */ 07854 /****************************************************************************/ 07855 struct CFLASH_tag { 07856 union { /* Module Configuration Register */ 07857 vuint32_t R; 07858 struct { 07859 vuint32_t EDC:1; 07860 vuint32_t:4; 07861 vuint32_t SIZE:3; 07862 vuint32_t:1; 07863 vuint32_t LAS:3; 07864 vuint32_t:3; 07865 vuint32_t MAS:1; 07866 vuint32_t EER:1; 07867 vuint32_t RWE:1; 07868 vuint32_t:1; 07869 vuint32_t:1; 07870 vuint32_t PEAS:1; 07871 vuint32_t DONE:1; 07872 vuint32_t PEG:1; 07873 vuint32_t:4; 07874 vuint32_t PGM:1; 07875 vuint32_t PSUS:1; 07876 vuint32_t ERS:1; 07877 vuint32_t ESUS:1; 07878 vuint32_t EHV:1; 07879 } B; 07880 } MCR; 07881 07882 union { /* LML Register */ 07883 vuint32_t R; 07884 struct { 07885 vuint32_t LME:1; 07886 vuint32_t:10; 07887 vuint32_t TSLK:1; 07888 vuint32_t:2; 07889 vuint32_t MLK:2; 07890 vuint32_t LLK:16; 07891 } B; 07892 } LML; 07893 07894 union { /* HBL Register */ 07895 vuint32_t R; 07896 struct { 07897 vuint32_t HBE:1; 07898 vuint32_t:23; 07899 vuint32_t HBLOCK:8; 07900 } B; 07901 } HBL; 07902 07903 union { /* SLML Register */ 07904 vuint32_t R; 07905 struct { 07906 vuint32_t SLE:1; 07907 vuint32_t:10; 07908 vuint32_t STSLK:1; 07909 vuint32_t:2; 07910 vuint32_t SMK:2; 07911 vuint32_t SLK:16; 07912 } B; 07913 } SLL; 07914 07915 union { /* LMS Register */ 07916 vuint32_t R; 07917 struct { 07918 vuint32_t:14; 07919 vuint32_t MSL:2; 07920 vuint32_t LSL:16; 07921 } B; 07922 } LMS; 07923 07924 union { /* High Address Space Block Select Register */ 07925 vuint32_t R; 07926 struct { 07927 vuint32_t:26; 07928 vuint32_t HSL:6; 07929 } B; 07930 } HBS; 07931 07932 union { /* Address Register */ 07933 vuint32_t R; 07934 struct { 07935 vuint32_t:9; 07936 vuint32_t ADD:20; 07937 vuint32_t:3; 07938 } B; 07939 } ADR; 07940 07941 union { /* CFLASH Configuration Register 0 */ 07942 vuint32_t R; 07943 struct { 07944 vuint32_t BK0_APC:5; 07945 vuint32_t BK0_WWSC:5; 07946 vuint32_t BK0_RWSC:5; 07947 vuint32_t BK0_RWWC2:1; 07948 vuint32_t BK0_RWWC1:1; 07949 vuint32_t B0_P1_BCFG:2; 07950 vuint32_t B0_P1_DPFE:1; 07951 vuint32_t B0_P1_IPFE:1; 07952 vuint32_t B0_P1_PFLM:2; 07953 vuint32_t B0_P1_BFE:1; 07954 vuint32_t BK0_RWWC0:1; 07955 vuint32_t B0_P0_BCFG:2; 07956 vuint32_t B0_P0_DPFE:1; 07957 vuint32_t B0_P0_IPFE:1; 07958 vuint32_t B0_P0_PFLM:2; 07959 vuint32_t B0_P0_BFE:1; 07960 } B; 07961 } PFCR0; 07962 07963 union { /* CFLASH Configuration Register 1 */ 07964 vuint32_t R; 07965 struct { 07966 vuint32_t BK1_APC:5; 07967 vuint32_t BK1_WWSC:5; 07968 vuint32_t BK1_RWSC:5; 07969 vuint32_t BK1_RWWC2:1; 07970 vuint32_t BK1_RWWC1:1; 07971 vuint32_t:6; 07972 vuint32_t B0_P1_BFE:1; 07973 vuint32_t BK1_RWWC0:1; 07974 vuint32_t:6; 07975 vuint32_t B1_P0_BFE:1; 07976 } B; 07977 } PFCR1; 07978 07979 union { /* cflash Access Protection Register */ 07980 vuint32_t R; 07981 struct { 07982 vuint32_t:6; 07983 vuint32_t ARBM:2; 07984 vuint32_t M7PFD:1; 07985 vuint32_t M6PFD:1; 07986 vuint32_t M5PFD:1; 07987 vuint32_t M4PFD:1; 07988 vuint32_t M3PFD:1; 07989 vuint32_t M2PFD:1; 07990 vuint32_t M1PFD:1; 07991 vuint32_t M0PFD:1; 07992 vuint32_t M7AP:2; 07993 vuint32_t M6AP:2; 07994 vuint32_t M5AP:2; 07995 vuint32_t M4AP:2; 07996 vuint32_t M3AP:2; 07997 vuint32_t M2AP:2; 07998 vuint32_t M1AP:2; 07999 vuint32_t M0AP:2; 08000 } B; 08001 } FAPR; 08002 08003 int32_t CFLASH_reserved0[5]; /* {0x003C-0x0028}/0x4 = 0x05 */ 08004 08005 union { /* User Test Register 0 */ 08006 vuint32_t R; 08007 struct { 08008 vuint32_t UTE:1; 08009 vuint32_t:7; 08010 vuint32_t DSI:8; 08011 vuint32_t:10; 08012 vuint32_t MRE:1; 08013 vuint32_t MRV:1; 08014 vuint32_t EIE:1; 08015 vuint32_t AIS:1; 08016 vuint32_t AIE:1; 08017 vuint32_t AID:1; 08018 } B; 08019 } UT0; 08020 08021 union { /* User Test Register 1 */ 08022 vuint32_t R; 08023 struct { 08024 vuint32_t DAI:32; 08025 } B; 08026 } UT1; 08027 08028 union { /* User Test Register 2 */ 08029 vuint32_t R; 08030 struct { 08031 vuint32_t DAI:32; 08032 } B; 08033 } UT2; 08034 08035 union { /* User Multiple Input Signature Register 0-4 */ 08036 vuint32_t R; 08037 struct { 08038 vuint32_t MS:32; 08039 } B; 08040 } UMISR[5]; 08041 08042 }; /* end of CFLASH_tag */ 08043 08044 /****************************************************************************/ 08045 /* MODULE : CRC */ 08046 /****************************************************************************/ 08047 struct CRC_SUB_tag { 08048 union { 08049 vuint8_t B[4]; /* Data buffer in Bytes (8 bits) */ 08050 vuint16_t H[2]; /* Data buffer in Half-words (16 bits) */ 08051 vuint32_t W; /* Data buffer in words (32 bits) */ 08052 struct { 08053 vuint32_t INV:1; 08054 vuint32_t SWAP:1; 08055 vuint32_t POLYG:1; 08056 vuint32_t:29; 08057 }BIT; 08058 } CRC_CFG; /* CRC Configuration Register */ 08059 08060 union { 08061 vuint8_t B[4]; /* Data buffer in Bytes (8 bits) */ 08062 vuint16_t H[2]; /* Data buffer in Half-words (16 bits) */ 08063 vuint32_t W; /* Data buffer in words (32 bits) */ 08064 } CRC_INP; /* CRC Input Register */ 08065 08066 union { 08067 vuint8_t B[4]; /* Data buffer in Bytes (8 bits) */ 08068 vuint16_t H[2]; /* Data buffer in Half-words (16 bits) */ 08069 vuint32_t W; /* Data buffer in words (32 bits) */ 08070 } CRC_CSTAT; /*CRC Current Status Register */ 08071 08072 union { 08073 vuint8_t B[4]; /* Data buffer in Bytes (8 bits) */ 08074 vuint16_t H[2]; /* Data buffer in Half-words (16 bits) */ 08075 vuint32_t W; /* Data buffer in words (32 bits) */ 08076 } CRC_OUTP; /* CRC Output Register */ 08077 08078 }; /* end of CRC_tag */ 08079 08080 struct CRC_tag { 08081 struct CRC_SUB_tag CNTX[2]; 08082 }; 08083 08084 /****************************************************************** 08085 | defines and macros (scope: module-local) 08086 |-----------------------------------------------------------------*/ 08087 /* Define instances of modules */ 08088 #define ADC_0 (*(volatile struct ADC_tag *) 0xFFE00000UL) 08089 #define ADC_1 (*(volatile struct ADC_tag *) 0xFFE04000UL) 08090 #define CAN_0 (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL) 08091 #define CAN_1 (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL) 08092 #define CAN_2 (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL) 08093 #define CAN_3 (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL) 08094 #define CAN_4 (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL) 08095 #define CAN_5 (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL) 08096 #define CANSP (*(volatile struct CANSP_tag *) 0xFFE70000UL) 08097 #define CFLASH (*(volatile struct CFLASH_tag *) 0xC3F88000UL) 08098 #define CGM (*(volatile struct CGM_tag *) 0xC3FE0000UL) 08099 #define CTU_0 (*(volatile struct CTU_tag *) 0xFFE0C000UL) 08100 #define CTU_1 (*(volatile struct CTU_tag *) 0xFFE10000UL) 08101 #define CTUL (*(volatile struct CTUL_tag *) 0xFFE64000UL) 08102 #define DCU (*(volatile struct DCU_tag *) 0xFFE7C000UL) 08103 #define DFLASH (*(volatile struct DFLASH_tag *) 0xC3F8C000UL) 08104 #define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL) 08105 #define DSPI_0 (*(volatile struct DSPI_tag *) 0xFFF90000UL) 08106 #define DSPI_1 (*(volatile struct DSPI_tag *) 0xFFF94000UL) 08107 #define DSPI_2 (*(volatile struct DSPI_tag *) 0xFFF98000UL) 08108 #define DSPI_3 (*(volatile struct DSPI_tag *) 0xFFF9C000UL) 08109 #define EBI (*(volatile struct EBI_tag *) 0xC3F84000UL) 08110 #define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL) 08111 #define EMIOS_0 (*(volatile struct EMIOS_tag *) 0xC3FA0000UL) 08112 #define EMIOS_1 (*(volatile struct EMIOS_tag *) 0xC3FA4000UL) 08113 #define ETIMER_0 (*(volatile struct ETIMER_tag *) 0xFFE18000UL) 08114 #define ETIMER_1 (*(volatile struct ETIMER_tag *) 0xFFE1C000UL) 08115 #define FCU (*(volatile struct FCU_tag *) 0xFFE6C000UL) 08116 #define FLEXPWM_0 (*(volatile struct FLEXPWM_tag *) 0xFFE24000UL) 08117 #define FLEXPWM_1 (*(volatile struct FLEXPWM_tag *) 0xFFE28000UL) 08118 #define FR (*(volatile struct FR_tag *) 0xFFFE0000UL) 08119 #define I2C_0 (*(volatile struct I2C_tag *) 0xFFE30000UL) 08120 #define I2C_1 (*(volatile struct I2C_tag *) 0xFFE34000UL) 08121 #define I2C_2 (*(volatile struct I2C_tag *) 0xFFE38000UL) 08122 #define I2C_3 (*(volatile struct I2C_tag *) 0xFFE3C000UL) 08123 #define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL) 08124 #define LCD (*(volatile struct LCD_tag *) 0xFFE74000UL) 08125 #define LINFLEX_0 (*(volatile struct LINFLEX_tag *) 0xFFE40000UL) 08126 #define LINFLEX_1 (*(volatile struct LINFLEX_tag *) 0xFFE44000UL) 08127 #define LINFLEX_2 (*(volatile struct LINFLEX_tag *) 0xFFE48000UL) 08128 #define LINFLEX_3 (*(volatile struct LINFLEX_tag *) 0xFFE4C000UL) 08129 #define MCM (*(volatile struct MCM_tag *) 0xFFF40000UL) 08130 #define ME (*(volatile struct ME_tag *) 0xC3FDC000UL) 08131 #define MPU (*(volatile struct MPU_tag *) 0xFFF10000UL) 08132 #define PCU (*(volatile struct PCU_tag *) 0xC3FE8000UL) 08133 #define PIT (*(volatile struct PIT_tag *) 0xC3FF0000UL) 08134 #define RGM (*(volatile struct RGM_tag *) 0xC3FE4000UL) 08135 #define RTC (*(volatile struct RTC_tag *) 0xC3FEC000UL) 08136 #define SAFEPORT (*(volatile struct FLEXCAN_tag *) 0xFFFE8000UL) 08137 #define SIU (*(volatile struct SIU_tag *) 0xC3F90000UL) 08138 #define SMC (*(volatile struct SMC_tag *) 0xFFE60000UL) 08139 #define SSCM (*(volatile struct SSCM_tag *) 0xC3FD8000UL) 08140 #define SSD_0 (*(volatile struct SSD_tag *) 0xFFE61000UL) 08141 #define SSD_1 (*(volatile struct SSD_tag *) 0xFFE61800UL) 08142 #define SSD_2 (*(volatile struct SSD_tag *) 0xFFE62000UL) 08143 #define SSD_3 (*(volatile struct SSD_tag *) 0xFFE62800UL) 08144 #define SSD_4 (*(volatile struct SSD_tag *) 0xFFE63000UL) 08145 #define SSD_5 (*(volatile struct SSD_tag *) 0xFFE63800UL) 08146 #define STM (*(volatile struct STM_tag *) 0xFFF3C000UL) 08147 #define SWT (*(volatile struct SWT_tag *) 0xFFF38000UL) 08148 #define WKUP (*(volatile struct WKUP_tag *) 0xC3F94000UL) 08149 #define CRC (*(volatile struct CRC_tag *) 0xFFE68000UL) 08150 08151 #ifdef __MWERKS__ 08152 #pragma pop 08153 #endif 08154 08155 #ifdef __cplusplus 08156 } 08157 #endif 08158 #endif /* ifdef _JDP_H */ 08159 /* End of file */
1.7.5.1 
